On some of the mvebu SoCs and due to internal BootROM issue, the CPU
initial jump code must be placed in the SRAM memory of the SoC. In
order to achieve this, we have to unmap the BootROM and at some
specific location where the BootROM was placed, create a dedicated
MBus window for the SRAM. This SRAM is initialized with a few
instructions of code that allows to jump to the real secondary CPU
boot address. The SRAM used is the Crypto engine one.

This work around is currently needed for booting SMP on Armada 375 Z1
and will be needed for cpuidle support on Armada 370. Instead of
duplicating the same code, this commit introduces a common function to
handle it: mvebu_setup_boot_addr_wa().
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1406120453-29291-4-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Sorting the headers in alphabetic order will help to reduce conflicts
when adding new headers later.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1406120453-29291-3-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

do_armada_370_xp_cpu_suspend() and armada_370_xp_pmsu_idle_prepare(),
have been merged into a single function called
armada_370_xp_pmsu_idle_enter() by the commit "bbb92284 ARM:
mvebu: slightly refactor/rename PMSU idle related functions", in
prepare for the introduction of the CPU hotplug support for Armada XP.

But for cpuidle the prepare function will be common to all the mvebu
SoCs that use the PMSU, while the suspend function will be specific to
each SoC. Keeping the prepare function separate will help reducing
code duplication while new SoC support is added.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1406120453-29291-2-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Currently, the coherency fabric support registers two bus notifiers;
one for platform, one for pci bus types, with the same notifier block.
However, this is illegal and can cause serious issues: the notifier
block is also a link in the notifier list and cannot be inserted twice.

This commit fixes this by using different notifier blocks (with the same
notifier callback) to set the platform and pci bus types notifiers.

Fixes: b0063aad ("ARM: mvebu: use hardware I/O coherency also for PCI devices")
Reported-by: NPaolo Pisati <p.pisati@gmail.com>
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1404826657-6977-1-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

In the inline asm part of the function armada_370_xp_pmsu_idle_enter()
the input operand was used. The intent here was to let the compiler
choose this register so it could do the optimization it
needed.

However an input operand is not supposed to be modified by the inline
asm code. This can lead to improper generated instructions.

In some case generated instruction the compiler made the choice to
reuse the same register to store the return value. But in the assembly
part this register was modified, so it can lead to return an wrong
value.

The fix is to use a clobber. Thanks to this the compiler will know
that the value of this register will be modified.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404483736-16938-1-git-send-email-gregory.clement@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The SMP boot on Armada 38x and Armada 375 Z1 is currently broken in
big-endian configurations, and this commit fixes it for both
platforms.

For Armada 375 Z1, the problem was in the
armada_375_smp_cpu1_enable_code part of the code that gets copied to
the Crypto SRAM as a work-around for an issue of the Z1 stepping. This
piece of code was not switching the CPU core to big-endian, and not
endian-swapping the value read from the Resume Address register (the
value is stored little-endian). Due to the introduction of the
conditional 'rev r1, r1' instruction, the offset between the 'ldr r0,
[pc, #4]' instruction and the value it was looking is different
between LE and BE configurations. To solve this, we instead use one
'adr' instruction followed by one 'ldr'.

For Armada 38x, the problem was simply that the CPU core was not
switched to big endian in the secondary CPU startup function.

This change was tested in LE and BE configurations on Armada 385,
Armada 375 Z1 and Armada 375 A0.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404228186-21203-1-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

On Marvell Armada XP, when a CPU comes back from deep idle state of
cpuidle, it restarts its execution at armada_370_xp_cpu_resume(),
which puts back the CPU into the coherency, and then calls the generic
cpu_resume() function.

While this works on little-endian configurations, it doesn't work on
big-endian configurations because the CPU restarts in little-endian,
and therefore must be switched back to big-endian to operate
properly. To achieve this, a 'setend be' instruction must be executed
in big-endian configurations. However, the ARM_BE8() macro that is
used to implement nice compile-time conditional for ARM LE vs. ARM BE8
is not easily usable in inline assembly.

Therefore, this patch moves the armada_370_xp_cpu_resume() C function,
which was anyway just a block of inline assembly, into a proper
pmsu_ll.S file, and adds the appropriate ARM_BE8(setend be)
instruction.

Without this patch, an Armada XP big endian configuration with cpuidle
enabled fails to boot, as it hangs as soon as one of the CPU hits the
deep idle state.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404130165-3593-1-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

'mvebu_cpu_reset_init' is local to this file.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Link: https://lkml.kernel.org/r/1403610235-22654-4-git-send-email-sachin.kamat@samsung.comSigned-off-by: NSachin Kamat <sachin.kamat@samsung.com>
Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

'armada_370_xp_cpu_pm_init' is local to this file.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Link: https://lkml.kernel.org/r/1403610235-22654-3-git-send-email-sachin.kamat@samsung.comSigned-off-by: NSachin Kamat <sachin.kamat@samsung.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

'armada_375_smp_cpu1_enable_wa' is local to this file.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Link: https://lkml.kernel.org/r/1403610235-22654-2-git-send-email-sachin.kamat@samsung.comSigned-off-by: NSachin Kamat <sachin.kamat@samsung.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

On Armada 38x it is possible to get the SoC Id and the revision
without using the PCI register. Accessing the PCI registers implies
enabling its clock and, because of the initialization issue, not
keeping them enable. So if possible it is better to avoid it.

Armada 370 and Armada XP provides the SoC ID values from the system
controller but not the revision.

Armada 375 provides both but the SoC ID value looks buggy (0x6660
instead of 0x6720).
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1403538128-27859-1-git-send-email-gregory.clement@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Instead of using -1 as error value, use a standard errno.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1403274953-21790-2-git-send-email-gregory.clement@free-electrons.comAcked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Commit 497a9230 ("ARM: mvebu:
implement L2/PCIe deadlock workaround") introduced some logic in
coherency.c to adjust the PL310 cache controller Device Tree node of
Armada 375 and Armada 38x platform to include the 'arm,io-coherent'
property if the system is running with hardware I/O coherency enabled.

However, with the L2CC driver cleanup done by Russell King, the
initialization of the L2CC driver has been moved earlier, and is now
part of the init_IRQ() ARM function in
arch/arm/kernel/irq.c. Therefore, calling coherency_init() in
->init_time() is now too late, as the Device Tree property gets added
too late (after the L2CC driver has been initialized).

In order to fix this, this commit removes the ->init_time() callback
use in board-v7.c and replaces it with an ->init_irq() callback. We
therefore no longer use the default ->init_irq() callback, but we now
use the default ->init_time() callback.

In this newly introduced ->init_irq() callback, we call irqchip_init()
which is the default behavior when ->init_irq() isn't defined, and
then do the initialization related to the coherency: SCU, coherency
fabric, and mvebu-mbus (which is needed to start secondary CPUs).
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-4-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

In preparation to a small re-organization of the initialization
sequence in board-v7.c, this commit moves the registration of the
custom external abort handler on Armada 375 later in the boot
sequence, and makes it more similar to the other quirks that we
already have. There is indeed no need to register this abort handler
particularly early, it simply needs to be registered before switching
to userspace.

In addition to this, this commit makes the registration of the custom
abort handler conditional on Armada 375 Z1, because Armada 375 A0 and
later iterations are not affected by the issue.

This commit was tested on both Armada 375 Z1 and Armada 375 A0
platforms.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-3-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Currently, the thermal quirk is skipped only if the SoC revision is known to be
one that does not need them, but if the SoC revision cannot be obtained, the
quirk is applied assuming it's needed.

However, this quirk must be applied only we are sure the SoC needs it, for it
breaks the thermal support if applied on a SoC that doesn't need it. The reason
for this is that the quirk consists in changing the thermal devicetree
compatible string and register offsets, to workaround a hardware bug in the
early SoC revision.

Such changes are wrong if the SoC is a new revision and doesn't need
the workaround. Therefore, this commit changes the behavior, by
requiring the SoC revision to be known in order to peform a quirk.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1402425283-24989-1-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

This commit implements CPU hotplug support for the Marvell Armada XP
platform. The CPU hotplug stub functions from hotplug.c are moved into
platsmp.c, as it doesn't make much sense to have a separate file just
for these two functions.

In addition, this commit:

 * Implements the ->cpu_die() function of SMP operations by calling
   armada_370_xp_pmsu_idle_enter() to enter the deep idle state for
   CPUs going offline.

 * Implements a dummy ->cpu_kill() function, simply needed for the
   kernel to know we have CPU hotplug support.

 * The armada_xp_boot_secondary() function makes sure to wake up the
   CPU if waiting in deep idle state by sending an IPI. This is
   because armada_xp_boot_secondary() is now used in two different
   situations: for the initial boot of secondary CPUs (where CPU reset
   deassert is used to wake up CPUs) and for CPU hotplug (where an IPI
   is used to take CPU out of deep idle).

 * At boot time, we exit from the idle state in the
   ->smp_secondary_init() hook.

This commit has been tested using CPU hotplug through sysfs
(/sys/devices/system/cpu/cpuX/online) and using kexec.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1401481098-23326-5-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The PMSU idle enter/exit functions will be needed for the CPU hotplug
implementation on Armada XP, so this commit removes their static
qualifier, and adds the appropriate prototypes in armada-370-xp.h.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1401481098-23326-4-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The CPU hotplug code will need to call into PMSU functions to enter
and exit from deep idle states. However, the deep idle state is
currently entered by a function called do_armada_370_xp_cpu_suspend()
whose name really suggests it's an internal function, but we need to
export it to other files in mach-mvebu.

Therefore, this commit:

 * Merges the code of do_armada_370_xp_cpu_suspend() into
   armada_370_xp_pmsu_idle_prepare(), into a single function called
   armada_370_xp_pmsu_idle_enter(), which prepares the PMSU for deep
   idle, and then enters the deep idle state. This code will be common
   to both cpuidle and CPU hotplug.

 * For symetry, it renames the armada_370_xp_pmsu_idle_restore()
   function to armada_370_xp_pmsu_idle_exit().

We also remove the 'noinline' qualifier for these functions, which
apparently had no reason to be here.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1401481098-23326-3-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

In preparation to the addition of CPU hotplug support for Armada XP,
and therefore moving the existing stub functions for hotplug support,
this commit removes the reference from the SMP implementation of
Armada 375/38x to the armada_xp_cpu_die() function. Proper CPU hotplug
support for Armada 375 and 38x will be implemented at a later point.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1401481098-23326-2-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

There is currently no DT binding for the CPLD which controls the LEDs
on the Net 2Big and Net 5Big. So use a platform device.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1401132591-26305-2-git-send-email-andrew@lunn.chTested-by: NSimon Guinot <simon.guinot@sequanux.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

The armada_370_xp_pmsu_idle_prepare() function is only used internally
to pmsu.c, so there's no reason to not use the static qualifier.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1401116474-31221-1-git-send-email-thomas.petazzoni@free-electrons.comAcked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

On Marvell Armada platforms, the PMSU (Power Management Service Unit)
controls a number of power management related activities, needed for
things like suspend/resume, CPU hotplug, cpuidle or even simply SMP.

Since cpuidle support was added for Armada XP, the pmsu.c file in
arch/arm/mach-mvebu/ calls the cpu_suspend() and cpu_resume() ARM
functions, which are only available when
CONFIG_ARM_CPU_SUSPEND=y. Therefore, configurations that have
CONFIG_ARM_CPU_SUSPEND disabled due to PM_SLEEP being disabled no
longer build properly, due to undefined references to cpu_suspend()
and cpu_resume().

To fix this, this patch simply ensures CONFIG_ARM_CPU_SUSPEND is
always enabled for Marvell EBU v7 platforms. Doing things in a more
fine-grained way would require a lot of #ifdef-ery in pmsu.c to
isolate the parts that use cpu_suspend()/cpu_resume(), and those parts
would anyway have been needed as soon as either one of suspend/resume,
CPU hotplug or cpuidle was enabled.
Reported-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402488397-31381-1-git-send-email-thomas.petazzoni@free-electrons.comAcked-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Currently the mvebu boards need to detect the SoC revision in order to apply
some quirks needed to workaround issues found on I2C and thermal controllers
present only in very early SoC.

This detection requires PCI address translation to work, so we need to
explicitly select OF_ADDRESS_PCI.

This can be considered a partial revert of the following commit, that
wrongly removed the option selection:

commit 55400f3a
Author: Rob Herring <robh@kernel.org>
Date:   Tue Apr 22 14:15:52 2014 -0500

    ARM: mvebu: clean-up unneeded kconfig selects
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1402347165-19988-1-git-send-email-ezequiel.garcia@free-electrons.comAcked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Russell King points out that my ARM merge (commit eb3d3ec5) was
broken wrt the arch/arm/mach-mvebu/board-v7.c file, leaving in a stale
l2x0_of_init() call (it's now handled by the DT description).

Which is kind of embarrassing, since I knew about it as it wasn't the
only file that had similar merge issues.  At least I got the other ones
right.
Reported-by: NRussell King <rmk@arm.linux.org.uk>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.
Acked-by: NJason Cooper <jason@lakedaemon.net>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

When targetting ARCH_MULTIPLATFORM, we may include support for SoCs with
PCI-capable devices (e.g. mach-virt with virtio-pci).

This patch allows PCI support to be selected for these SoCs by selecting
CONFIG_MIGHT_HAVE_PCI when CONFIG_ARCH_MULTIPLATFORM=y and removes the
individual selections from multi-platform enabled SoCs.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

They're u32, they're not unsigned long.  The UL suffix is not required
here.
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

In the refactoring of the coherency fabric assembly code, a function
called ll_get_cpuid() was created to factorize common logic between
functions adding CPU to the SMP coherency group, enabling and
disabling the coherency.

However, the name of the function is highly misleading: ll_get_cpuid()
makes one think tat it returns the ID of the CPU, i.e 0 for CPU0, 1
for CPU1, etc. In fact, this is not at all what this function returns:
it returns a CPU mask for the current CPU, usable for the coherency
fabric configuration and control registers.

Therefore this commit renames this function to
ll_get_coherency_cpumask(), and adds additional comments on top of the
function to explain in more details what it does, and also how the
endianess issue is handled.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400762882-10116-5-git-send-email-thomas.petazzoni@free-electrons.comAcked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

This commit makes no functional change, it only improves a bit the
various code comments in mach-mvebu/coherency_ll.S, by fixing a few
typos and adding a few more details.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400762882-10116-4-git-send-email-thomas.petazzoni@free-electrons.comAcked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

This commit does not make any functional change, it only fixes the
indentation of a few assembly instructions in
arch/arm/mach-mvebu/coherency_ll.S.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400762882-10116-3-git-send-email-thomas.petazzoni@free-electrons.comAcked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

As part of the introduction of the cpuidle support for Armada XP, the
coherency code was significantly reworked, especially in the
coherency_ll.S file. However, when the ll_get_cpuid function was
created, the big-endian specific code that switches the endianess of
the register was not updated properly.

This patch fixes this code, and therefore makes big endian systems
bootable again.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400762882-10116-2-git-send-email-thomas.petazzoni@free-electrons.com
Fixes: 2e8a5942 ("ARM: mvebu: Split low level functions to manipulate HW coherency")
Reported-by: NKevin Hilman <khilman@linaro.org>
Cc: Kevin Hilman <khilman@linaro.org>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Commit b0063aad ("ARM: mvebu: use hardware I/O coherency also for
PCI devices") added a reference to the pci_bus_type variable, but this
variable is only available when CONFIG_PCI is enabled. Therefore,
there is now a build failure in !CONFIG_PCI situations.

This commit fixes that by enclosing the entire initcall into a
IS_ENABLED(CONFIG_PCI) condition.
Reported-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400598783-706-1-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The Marvell Armada 375 and Armada 38x SOCs, which use the Cortex-A9
CPU core, the PL310 cache and the Marvell PCIe hardware block are
affected a L2/PCIe deadlock caused by a system erratum when hardware
I/O coherency is used.

This deadlock can be avoided by mapping the PCIe memory areas as
strongly-ordered (note: MT_UNCACHED is strongly-ordered), and by
removing the outer cache sync done in software. This is implemented in
this patch by:

 * Registering a custom arch_ioremap_caller function that allows to
   make sure PCI memory regions are mapped MT_UNCACHED.

 * Adding at runtime the 'arm,io-coherent' property to the PL310 cache
   controller. This cannot be done permanently in the DT, because the
   hardware I/O coherency can only be enabled when CONFIG_SMP is
   enabled, in the current kernel situation.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400165974-9059-4-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Since the beginning of the introduction of hardware I/O coherency
support for Armada 370 and Armada XP, the special DMA operations
should have applied to all DMA capable devices. Unfortunately, while
the original code properly took into account platform devices, it
didn't take into account PCI devices, which can also be DMA masters.

This commit fixes that by registering a bus notifier on pci_bus_type,
to register our custom DMA operations, like is already done for
platform devices. While doing this, we also rename
mvebu_hwcc_platform_notifier() to mvebu_hwcc_notifier() and
mvebu_hwcc_platform_nb to mvebu_hwcc_nb because they are no longer
specific to platform devices.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399997070-11434-1-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Since the mvebu-soc-id code in mach-mvebu/ was introduced, several
users have noticed a regression: the PCIe card connected in the first
PCIe interface is not detected properly.

This is due to the fact that the mvebu-soc-id code enables the PCIe
clock of the first PCIe interface, reads the SoC device ID and
revision number (yes this information is made available as part of
PCIe registers), and then disables the clock. However, by doing this,
we gate the clock and therefore loose the complex PCIe configuration
that was done by the bootloader.

Unfortunately, as of today, the kernel is not capable of doing this
complex configuration by itself, so we really need to keep the PCIe
clock enabled. However, we don't want to keep it enabled
unconditionally: if the PCIe interface is not enabled or PCI support
is not compiled into the kernel, there is no reason to keep the PCIe
clock running.

This issue was discussed with Kevin Hilman, and the suggested solution
was to make the mvebu-soc-id code keep the clock enabled in case it
will be needed for PCIe. This is therefore the solution implemented in
this patch.

Long term, we hope to make the kernel more capable in terms of PCIe
configuration for this platform, which will anyway be needed to
support the compilation of the PCIe host controller driver as a
module. In the mean time however, we don't have much other choice than
to implement the currently proposed solution.
Reported-by: NNeil Greatorex <neil@fatboyfat.co.uk>
Cc: Neil Greatorex <neil@fatboyfat.co.uk>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Kevin Hilman <khilman@linaro.org>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399903900-29977-3-git-send-email-thomas.petazzoni@free-electrons.com
Fixes: af8d1c63 ("ARM: mvebu: Add support to get the ID and the revision of a SoC")
Cc: <stable@vger.kernel.org> # 3.14+: 42a18d1c: ARM: mvebu: mvebu-soc-id: add missing clk_put() call
Cc: <stable@vger.kernel.org> # 3.14+
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Tested-by: NWilly Tarreau <w@1wt.eu>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

The mvebu-soc-id code in mach-mvebu/ needs to enable a clock to read
the SoC device ID and revision number. To do so, it does a clk_get(),
then a clk_prepare_enable(), reads the value, and disables the clock
with clk_disable_unprepare(). However, it forgets to clk_put() the
clock. This commit fixes this issue.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399903900-29977-2-git-send-email-thomas.petazzoni@free-electrons.com
Cc: <stable@vger.kernel.org> # 3.14+
Fixes: af8d1c63 ("ARM: mvebu: Add support to get the ID and the revision of a SoC")
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Tested-by: NWilly Tarreau <w@1wt.eu>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

When compiling for multiplatform for both ARMv6 and ARMv7, the default compiler
flags are for ARMv6, and we will get:

  /tmp/ccwDEzd0.s: Assembler messages:
  /tmp/ccwDEzd0.s:639: Error: selected processor does not support ARM mode `isb '
  /tmp/ccwDEzd0.s:645: Error: selected processor does not support ARM mode `isb '
  /tmp/ccwDEzd0.s:646: Error: selected processor does not support ARM mode `dsb '
  /tmp/ccwDEzd0.s:695: Error: selected processor does not support ARM mode `isb '
  make[1]: *** [arch/arm/mach-mvebu/pmsu.o] Error 1

Fix this in a similar manner than done previously in commit
72533b77, by specifying ARMv7 flags for pmsu.o.
Signed-off-by: NVincent Stehlé <vincent.stehle@laposte.net>
Link: https://lkml.kernel.org/r/1399407782-29091-1-git-send-email-vincent.stehle@laposte.net
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

The Armada 375 coherency workaround only needs to be applied to the Z1
revision of the SoC. The A0 and later revisions have been fixed, and
no longer need this workaround.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399302326-6917-6-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The Armada 375 SMP workaround only needs to be applied to the Z1
revision of the SoC. The A0 and later revisions have been fixed, and
no longer need this workaround.

Note that the initialization of the SMP workaround is delayed from
->smp_prepare_cpus() to ->smp_boot_secondary() because when
->smp_prepare_cpus() is called, the early initcalls have not be
called, so the mvebu-soc-id mechanism is not operational. Since the
workaround is anyway not needed before the secondary CPU is started,
we can delay its implementation until the ->smp_boot_secondary() call.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399302326-6917-5-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Now that we have access to Armada 375 A0 platforms, we can add the
corresponding revision definition in mvebu-soc-id.h.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399302326-6917-4-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>