Since the LED modes mapping is no longer hardcoded inside the leds-ns2
driver, then it must be provided through the modes-map property in the
ns2-leds nodes.
Signed-off-by: NVincent Donnefort <vdonnefort@gmail.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJacek Anaszewski <j.anaszewski@samsung.com>

The base addresses for the Ux500 PRCC controllers are hardcoded,
let's move them to the clock node in the device tree and delete
the constants.

Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NOlof Johansson <olof@lixom.net>
Acked-by: NMichael Turquette <mturquette@baylibre.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We're removing struct clk from the clk provider API, so switch to
clk_get_rate() and clk_hw_get_rate() here appropriately.
Acked-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

PTR_ERR should access the value just tested by IS_ERR.

The semantic patch that makes this change is available
in scripts/coccinelle/tests/odd_ptr_err.cocci.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Specify how the GPIOs map to the pins in Tegra SoCs, so the dependency is
explicit.
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Current base address is wrong by 0x04 bytes for AHB bus device as shown
in dmesg:

	tegra-ahb 6000c004.ahb: incorrect AHB base address in DT data - enabling workaround

To correct old DTBs, commit ce7a10b0 ("ARM: 8334/1: amba: tegra-ahb:
detect and correct bogus base address") checks for the low bit of the
base address and removes theses 0x04 bytes at runtime.

This patch fixes the original DTS, so upstream version doesn't need the
workaround of the base address.

As both addresses are valid, this patch doesn't break compatibility.

Tested on tegra20-paz00 (aka ac100).
Signed-off-by: NNicolas Chauvet <kwizart@gmail.com>
Reviewed-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This patch modifies the device tree for Tegra124 based devices to enable
the Cortex A15 PMU. The interrupt numbers are taken from NVIDIA Tegra K1
TRM (DP-06905-001_v03p). This patch was tested on a Jetson TK1.
Signed-off-by: NKyle Huey <khuey@kylehuey.com>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the device-tree node for the GK20A GPU and leave it disabled.
It is the responsibility of the bootloader to enable it if the
VPR registers have been programmed such that the GPU can operate.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the device-tree node for the GK20A GPU and leave it disabled.
It is the responsibility of the bootloader to enable it if the
VPR registers have been programmed such that the GPU can operate.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>

Nouveau can make use of the IOMMU to make physical appear linear in the
GPU address space.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Specify the CPU voltage regulator for the cpufreq driver.
Signed-off-by: NTuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: NMikko Perttunen <mikko.perttunen@kapsi.fi>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Tegra124 cpufreq driver relies on certain clocks being present
in the /cpus/cpu@0 node.
Signed-off-by: NTuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: NMikko Perttunen <mikko.perttunen@kapsi.fi>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the board-specific properties of the DFLL for the Jetson TK1 board.
On this board, the DFLL will take control of the sd0 regulator on the
on-board AS3722 PMIC.
Signed-off-by: NTuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: NMikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: NMichael Turquette <mturquette@linaro.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The DFLL clocksource is a separate IP block from the usual
clock-and-reset controller, so it gets its own device tree node.
Signed-off-by: NTuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: NMikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: NMichael Turquette <mturquette@linaro.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

We should call phy_register_fixup_for_uid() only when CONFIG_PHYLIB
is built-in, otherwise we get the following link error when building
allmodconfig:

arch/arm/mach-imx/built-in.o: In function `imx6ul_init_machine':
:(.init.text+0xa714): undefined reference to `phy_register_fixup_for_uid'

This is the same approach done in mach-imx6q.c and mach-imx6sx.c.
Reported-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NShawn Guo <shawnguo@kernel.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Signed-off-by: NMoritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Since v3.18, attempts to deliver IRQ0 are rejected, breaking orion5x.
Fix this by increasing all interrupts by one, as did 5d6bed2a for
dove. Also, force MULTI_IRQ_HANDLER for all orion platforms (including
dove) as the specific handler is needed to shift back IRQ numbers by
one.

[gregory.clement@free-electrons.com]: moved the select
MULTI_IRQ_HANDLER from PLAT_ORION_LEGACY to ARCH_ORION5X as it broke
the build for dove.

Fixes: a71b092a ("ARM: Convert handle_IRQ to use __handle_domain_irq")
Signed-off-by: NBenjamin Cama <benoar@dolka.fr>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Cc: <stable@vger.kernel.org>
Tested-by: NDetlef Vollmann <dv@vollmann.ch>

This SoC is integrated with 4 Cortex-A9 cores.  The GIC bindings
document says that the bits[15:8] of the 3rd cell of the interrupts
property represents PPI interrupt CPU mask.  Because the timer
interrupts are wired to all of the 4 cores, bits[15:8] should be set
to 0xf.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

When getting translated from a downstream device tree that used slightly
different DT bindings, these regulators got labeled with the
"on-in-suspend" state, when they were actually supposed to be turned off
for S3 suspend. This was harmless, but not intentional, AFAICT.

Let's turn them off to get the optimal power state.
Signed-off-by: NBrian Norris <briannorris@chromium.org>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This DTS file was submitted with non-upstream bindings. I happened
across this while reviewing the jaq DTS.
Signed-off-by: NBrian Norris <briannorris@chromium.org>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

ARM now uses pci_bus->msi to store the msi_controller pointer, so we don't
need to save it in struct pci_sys_data, and we don't need to implement
pcibios_msi_controller() to get it out of pci_sys_data.

Remove msi_controller from struct pci_sys_data and
pcibios_msi_controller().

[bhelgaas: changelog, split into separate patch]
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NJingoo Han <jingoohan1@gmail.com>

ARM previously stored the msi_controller pointer in its sysdata, struct
pci_sys_data, and implemented pcibios_msi_controller() to retrieve it.
That made PCI host controller drivers specific to ARM because they had to
put the msi_controller pointer in the ARM-specific pci_sys_data.

There is now a generic mechanism, pci_scan_root_bus_msi(), for giving the
msi_controller pointer to the PCI core.  Use this for all ARM systems and
for the DesignWare and Xilinx PCI host controller drivers.

This removes an ARM dependency from the DesignWare, DRA7xx, EXYNOS, i.MX6,
Keystone, Layerscape, SPEAr13xx, and Xilinx drivers.

[bhelgaas: changelog, split into separate patch]
Suggested-by: NRussell King <linux@arm.linux.org.uk>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jingoohan1@gmail.com>
CC: Pratyush Anand <pratyush.anand@gmail.com>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Simon Horman <horms@verge.net.au>
CC: Russell King <linux@arm.linux.org.uk>
CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
CC: Thierry Reding <thierry.reding@gmail.com>
CC: Michal Simek <michal.simek@xilinx.com>
CC: Marc Zyngier <marc.zyngier@arm.com>

In the ARM PCI bios32 layer, failures to dynamically allocate pci_sys_data
for a PCI bus, or a PCI bus scan failure have to be considered serious
warnings but they should not trigger a system panic so that at least the
system is given a chance to be debugged.

This patch replaces the panic statements with WARN() messages to improve
error reporting in the ARM PCI bios32 layer.
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NJingoo Han <jingoohan1@gmail.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Marc Zyngier <marc.zyngier@arm.com>

The conversion of the wakeupgen irqchip to hierarchical irq domains
failed to provide a mechanism to properly set the trigger type of an
interrupt.

The wakeupgen irq chip itself has no mechanism and therefor no
irq_set_type() callback. The code before the conversion relayed the
trigger configuration directly to the underlying GIC.

Restore the correct behaviour by setting the wakeupgen irq_set_type
callback to irq_chip_set_type_parent(). This propagates the
set_trigger() call to the underlying GIC irqchip.

[ tglx: Massaged changelog ]

Fixes: 7136d457 ('ARM: omap: convert wakeupgen to stacked domains')
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: <linux@arm.linux.org.uk>
Cc: <nsekhar@ti.com>
Cc: <jason@lakedaemon.net>
Cc: <balbi@ti.com>
Cc: <linux-arm-kernel@lists.infradead.org>
Cc: <marc.zyngier@arm.com>
Cc: stable@vger.kernel.org # 4.1
Link: http://lkml.kernel.org/r/1439554830-19502-5-git-send-email-grygorii.strashko@ti.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

Without this, the multi_v7_defconfig kernel cannot boot all CPUs
nor do deep cpuidle power saving on a TC2 board.
Signed-off-by: NNicolas Pitre <nico@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The sp810 clk driver is calling the clk consumer APIs from
clk_prepare ops to change the parent to a 1 MHz fixed rate clock
for each of the clocks that the driver provides. Use
assigned-clock-parents for this instead of doing it in the driver
to avoid using the consumer API in provider code. This also
allows us to remove the usage of clk provider APIs that take a
struct clk as an argument from the sp810 driver.

Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Tested-by: NSudeep Holla <sudeep.holla@arm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

U-Boot is often used to boot the kernel on ARM boards, but uImage
is not built by "make all", so we are often inclined to do
"make all uImage" to generate DTBs, modules and uImage in a single
command, but we should notice a pitfall behind it.  In fact,
"make all uImage" could generate an invalid uImage if it is run with
the parallel option (-j).

You can reproduce this problem with the following procedure:

[1] First, build "all" and "uImage" separately.
    You will get a valid uImage

  $ git clean -f -x -d
  $ export CROSS_COMPILE=<your-tools-prefix>
  $ make -s -j8 ARCH=arm multi_v7_defconfig
  $ make -s -j8 ARCH=arm all
  $ make -j8 ARCH=arm UIMAGE_LOADADDR=0x80208000 uImage
    CHK     include/config/kernel.release
    CHK     include/generated/uapi/linux/version.h
    CHK     include/generated/utsrelease.h
  make[1]: `include/generated/mach-types.h' is up to date.
    CHK     include/generated/timeconst.h
    CHK     include/generated/bounds.h
    CHK     include/generated/asm-offsets.h
    CALL    scripts/checksyscalls.sh
    CHK     include/generated/compile.h
    Kernel: arch/arm/boot/Image is ready
    Kernel: arch/arm/boot/zImage is ready
    UIMAGE  arch/arm/boot/uImage
  Image Name:   Linux-4.2.0-rc5-00156-gdd2384a7-d
  Created:      Sat Aug  8 23:21:35 2015
  Image Type:   ARM Linux Kernel Image (uncompressed)
  Data Size:    6138648 Bytes = 5994.77 kB = 5.85 MB
  Load Address: 80208000
  Entry Point:  80208000
    Image arch/arm/boot/uImage is ready
  $ ls -l arch/arm/boot/*Image
  -rwxrwxr-x 1 masahiro masahiro 13766656 Aug  8 23:20 arch/arm/boot/Image
  -rw-rw-r-- 1 masahiro masahiro  6138712 Aug  8 23:21 arch/arm/boot/uImage
  -rwxrwxr-x 1 masahiro masahiro  6138648 Aug  8 23:20 arch/arm/boot/zImage

[2] Update some source file(s)

  $ touch init/main.c

[3] Then, re-build "all" and "uImage" simultaneously.
    You will get an invalid uImage at random.

  $ make -j8 ARCH=arm UIMAGE_LOADADDR=0x80208000 all uImage
    CHK     include/config/kernel.release
    CHK     include/generated/uapi/linux/version.h
    CHK     include/generated/utsrelease.h
  make[1]: `include/generated/mach-types.h' is up to date.
    CHK     include/generated/timeconst.h
    CHK     include/generated/bounds.h
    CHK     include/generated/asm-offsets.h
    CALL    scripts/checksyscalls.sh
    CC      init/main.o
    CHK     include/generated/compile.h
    LD      init/built-in.o
    LINK    vmlinux
    LD      vmlinux.o
    MODPOST vmlinux.o
    GEN     .version
    CHK     include/generated/compile.h
    UPD     include/generated/compile.h
    CC      init/version.o
    LD      init/built-in.o
    KSYM    .tmp_kallsyms1.o
    KSYM    .tmp_kallsyms2.o
    LD      vmlinux
    SORTEX  vmlinux
    SYSMAP  System.map
    OBJCOPY arch/arm/boot/Image
    Building modules, stage 2.
    Kernel: arch/arm/boot/Image is ready
    GZIP    arch/arm/boot/compressed/piggy.gzip
    AS      arch/arm/boot/compressed/piggy.gzip.o
    Kernel: arch/arm/boot/Image is ready
    LD      arch/arm/boot/compressed/vmlinux
    GZIP    arch/arm/boot/compressed/piggy.gzip
    OBJCOPY arch/arm/boot/zImage
    Kernel: arch/arm/boot/zImage is ready
    UIMAGE  arch/arm/boot/uImage
  Image Name:   Linux-4.2.0-rc5-00156-gdd2384a7-d
  Created:      Sat Aug  8 23:23:14 2015
  Image Type:   ARM Linux Kernel Image (uncompressed)
  Data Size:    26472 Bytes = 25.85 kB = 0.03 MB
  Load Address: 80208000
  Entry Point:  80208000
    Image arch/arm/boot/uImage is ready
    MODPOST 192 modules
    AS      arch/arm/boot/compressed/piggy.gzip.o
    LD      arch/arm/boot/compressed/vmlinux
    OBJCOPY arch/arm/boot/zImage
    Kernel: arch/arm/boot/zImage is ready
  $ ls -l arch/arm/boot/*Image
  -rwxrwxr-x 1 masahiro masahiro 13766656 Aug  8 23:23 arch/arm/boot/Image
  -rw-rw-r-- 1 masahiro masahiro    26536 Aug  8 23:23 arch/arm/boot/uImage
  -rwxrwxr-x 1 masahiro masahiro  6138648 Aug  8 23:23 arch/arm/boot/zImage

Please notice the uImage is extremely small when this issue is
encountered.  Besides, "Kernel: arch/arm/boot/zImage is ready" is
displayed twice, before and after the uImage log.

The root cause of this is the race condition between zImage and
uImage.  Actually, uImage depends on zImage, but the dependency
between the two is only described in arch/arm/boot/Makefile.
Because arch/arm/boot/Makefile is not included from the top-level
Makefile, it cannot know the dependency between zImage and uImage.

Consequently, when we run make with the parallel option, Kbuild
updates vmlinux first, and then two different threads descends into
the arch/arm/boot/Makefile almost at the same time, one for updating
zImage and the other for uImage.  While one thread is re-generating
zImage, the other also tries to update zImage before creating uImage
on top of that.  zImage is overwritten by the slower thread and then
uImage is created based on the half-written zImage.

This is the reason why "Kernel: arch/arm/boot/zImage is ready" is
displayed twice, and a broken uImage is created.

The same problem could happen on bootpImage.

This commit adds dependencies among Image, zImage, uImage, and
bootpImage to arch/arm/Makefile, which is included from the
top-level Makefile.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The mmap semaphore should not be taken when page faults are disabled.
Since pagefault_disable() no longer disables preemption, we now need
to use faulthandler_disabled() in place of in_atomic().
Signed-off-by: NNicolas Pitre <nico@linaro.org>
Tested-by: NMark Salter <msalter@redhat.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This change is a code reorganization. Here we introduce
serial_imx_enable_wakeup() helper function to do
the job of configuring and preparing wakeup sources
on imx serial device. The idea is to allow other
parts of the code to call this function whenever
the device is known to go to idle.

Cc: Fabio Estevam <festevam@gmail.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jslaby@suse.com>
Cc: linux-serial@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: NEduardo Valentin <edubezval@gmail.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

SPI Davinci driver has been updated to allow SOCs to specify their minimum
prescale value. Update the various SOCs board files that use this driver with
their proper prescaler limit.
Acked-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Add Tegra-specific configuration options to multi_v7_defconfig:

  * HDA controller and codec support
  * Watchdog support
  * Nouveau (for GK20A GPU) support
Signed-off-by: NThierry Reding <treding@nvidia.com>

  * CPU frequency scaling for Tegra124
  * Nouveau (for GK20A GPU) support
Signed-off-by: NThierry Reding <treding@nvidia.com>

Currently mdio bindings are defined in keystone.dtsi and this results
in incorrect unit address for the node on K2E and K2L SoCs. Fix this
by moving them to SoC specific DTS file.
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <ssantosh@kernel.org>

Currently the MDIO clock is pointing to clkpa instead of clkcpgmac.
MDIO is part of the ethss and the clock should be clkcpgmac.
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <ssantosh@kernel.org>

This callback is expected to do the same as enter() but it has to
guarantee that interrupts aren't enabled at any point in its execution,
as the tick is frozen.

It will be called when the system goes to suspend-to-idle and will
reduce power usage because CPUs won't be awaken for unnecessary IRQs.

By setting the CPUIDLE_FLAG_TIMER_STOP flag, we can reuse the same code
for both the enter() and enter_freeze() callbacks.
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This is only relevant on Tegra114 and Tegra124, because earlier Tegra
generations used Cortex-A9 without secure extensions.
Signed-off-by: NThierry Reding <treding@nvidia.com>

All the EP93xx boards exclusively use modedb to look up video
modes from the command line. Root out the parametrization of
custom video modes from the platform data and board files
and simplify the driver.

Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Reviewed-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This is unnecessary since commit 02b4e275 ("ARM: v7 setup
function should invalidate L1 cache").
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

CONFIG_ARM_AT91_ETHER doesn't exist anymore, both drivers have been merged
in the macb driver.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This patch adds drm atmel lcdc, simple panel and backlight options.
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>