Due to problems at cam.org, my nico@cam.org email address is no longer
valid.  FRom now on, nico@fluxnic.net should be used instead.
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

This patch allows otpinfo for CFI >= 1.0 and burst read for CFI >= 1.1.

references:
1.0:	http://www.datasheetcatalog.org/datasheets2/81/816884_1.pdf

1.1:	http://milkymist.org/doc/MT28F640J3.pdf
	http://www.delorie.com/agenda/specs/29066709.pdfSigned-off-by: NDaniel Ribeiro <drwyrm@gmail.com>
Acked-by: NNicolas Pitre <nico@cam.org>
Signed-off-by: NArtem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This chip reports CFI 1.3, but the CFI PRI is like CFI 1.1. Add a quirk
to pass probe on this chip.

This patch depends on "MTD: CFI 1.0 and CFI 1.1"
Signed-off-by: NDaniel Ribeiro <drwyrm@gmail.com>
Acked-by: NNicolas Pitre <nico@cam.org>
Signed-off-by: NArtem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Add SST39SF040 chip (like SST39SF020A but bigger - 4Mbit).
Signed-off-by: NMichał Mirosław <mirq-linux@rere.qmqm.pl>
Signed-off-by: NArtem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Prevent NUMONYX M29W128G memories from using write buffer,
because it doesn't work properly.
Signed-off-by: NDarius Augulis <augulis.darius@gmail.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Present backing device capabilities for MTD character device files to allow
NOMMU mmap to do direct mapping where possible.
Signed-off-by: NDavid Howells <dhowells@redhat.com>
Tested-by: NBernd Schmidt <bernd.schmidt@analog.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NYegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

If the inval_cache_and_wait_for_operation() is re-entered by write operation when erase
operation is in progress, the chip->erase_suspended will be cleared, this cause the erase
timeo is not reset and will result time out error for erase.
Signed-off-by: NGraff Yang <graff.yang@gmail.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Which means if inftl or similar are loaded with it (which is a dumb thing
to do admittedly) it may oops.

Closes #8108

[dwmw2: change error to -EROFS to match write-protected flash]
Signed-off-by: NAlan Cox <alan@redhat.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

The NOR Flash memory K8P2815UQB from Samsung uses the major version
number '0'. Add a quirk to cope with it.
Signed-off-by: NWolfgang Grandegger <wg@grandegger.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

MTD internal API presently uses 32-bit values to represent
device size.  This patch updates them to 64-bits but leaves
the external API unchanged.  Extending the external API
is a separate issue for several reasons.  First, no one
needs it at the moment.  Secondly, whether the implementation
is done with IOCTLs, sysfs or both is still debated.  Thirdly
external API changes require the internal API to be accepted
first.

Note that although the MTD API will be able to support 64-bit
device sizes, existing drivers do not and are not required
to do so, although NAND base has been updated.

In general, changing from 32-bit to 64-bit values cause little
or no changes to the majority of the code with the following
exceptions:
    	- printk message formats
    	- division and modulus of 64-bit values
    	- NAND base support
	- 32-bit local variables used by mtdpart and mtdconcat
	- naughtily assuming one structure maps to another
	in MEMERASE ioctl
Signed-off-by: NAdrian Hunter <ext-adrian.hunter@nokia.com>
Signed-off-by: NArtem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

For "unlock" cycles to 16bit devices in 8bit compatibility mode we need
to use the byte addresses 0xaaa and 0x555. These effectively match
the word address 0x555 and 0x2aa, except the latter has its low bit set.

Most chips don't care about the value of the 'A-1' pin in x8 mode,
but some -- like the ST M29W320D -- do. So we need to be careful to
set it where appropriate.

cfi_send_gen_cmd is only ever passed addresses where the low byte
is 0x00, 0x55 or 0xaa. Of those, only addresses ending 0xaa are
affected by this patch, by masking in the extra low bit when the device
is known to be in compatibility mode.

[dwmw2: Do it only when (cmd_ofs & 0xff) == 0xaa]
v4: Fix  stupid typo in cfi_build_cmd_addr that failed to compile
    I'm writing this patch way to late at night.
v3: Bring all of the work back into cfi_build_cmd_addr
    including calling of map_bankwidth(map) and cfi_interleave(cfi)
    So every caller doesn't need to.
v2: Only modified the address if we our device_type is larger than our
    bus width.

Cc: stable@kernel.org
Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

The CFI information read from AT49BV6416 lists the erase regions in the
wrong order, causing problems when trying to erase or update the first
or last 64KiB block.

Work around this by inverting the "top boot" flag, which will
effectively reverse the order of the erase regions.

This chip is obsolete, but it's used in some existing designs.
Signed-off-by: NHåvard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This patch adds TopBottom detection for most Macronix chips with CFI V1.0.

The main purpose of this patch is to add detection of the MX29LV400C B
used on the LaCie Ethernet Disk mini V2 NAS.

It detects the following parts correctly:-
MX28F640C3B T
MX29LV002C  B
MX29LV002NC B
MX29LV004C  T
MX29LV400C  T/B
MX29LV800C  T/B
MX29LV160C  T/B
MX29SL800C  T/B
MX29SL802C  T/B

It detects the following uniform part as bottom but it should work
correctly:-
MX29LV040C

For T parts it causes the erase block table to be reversed correctly.
For other parts it avoids the bogus "Assuming top" message.

It does not detect the following correctly:-
MX28F640C3B B
MX29LV002C  T
MX29LV002NC T
MX29LV004C  B
MX29SL400C  T/B
MX29SL402C  T/B

If desired I could supply a more complicated patch to handle these as
well.

Only the MX29LV400C B has been physically tested; others were checked
against their data sheets.
Signed-off-by: NChristopher Moore <moore@free.fr>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

The patch fixes CFI issue with multipartitional devices leading to the 
set of errors or even deadlock. The problem is CFI FL_SYNCING state race 
with flash operations (e.g. erase suspend). It is reproduced by running 
intensive writes on one JFFS2 partition and simultaneously performing 
mount/unmount cycle on another partition of the same chip.
Signed-off-by: NAlexander Belyakov <abelyako@googlemail.com>
Acked-by: NNicolas Pitre <nico@cam.org>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

It requires cfi_qry_mode_on(), which is in cfi_util.c

Reported by Russell King
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

They need to be exported, so let's give them less generic-sounding names
while we're at it.

Original export patch, along with the suggestion about the nomenclature,
from Stephen Rothwell.
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Timeouts are currently given by the typical operation time times 8.
It works in the general well-behaved case but not when an erase block is
failing. For erase operations, it seems that a failing erase block will
keep the device state machine in erasing state until the vendor
specified maximum timeout period has passed. By this time the driver
would have long since timed out, left erasing state and attempted
further operations which all fail. This patch implements timeouts using
values from the CFI Query structure when available.
The patch also sets a longer timeout for locking operations. The current
value used for locking/unlocking given by 1000000/HZ microseconds is too
short for devices like J3 and J5 Strataflash which have a typical clear
lock-bits time of 0.5 seconds.
Signed-off-by: NAnders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

There are some CFI chips which require non standard procedures to get 
into QRY mode. The possible way to support them would be trying 
different modes till QRY will be read. This patch introduce two new 
functions qry_mode_on qry_mode_off. qry_mode_on tries different commands 
in order switch chip into QRY mode.

So if we have one more "odd" chip - we just could add several lines to 
qry_mode_on. Also using these functions remove unnecessary code 
duplicaton in porbe procedure.

Currently there are two "odd" cases
1. Some old intel chips which require 0xFF before 0x98
2. ST M29DW chip which requires 0x98 to be sent at 0x555 (according to
CFI should be 0x55)

This patch is partialy based on the patch from Uwe
(see "[PATCH 2/4] [RFC][MTD] cfi_probe: remove Intel chip workaround"
thread )
Signed-off-by: NAlexey Korolev <akorolev@infradead.org>
Signed-off-by: NAlexander Belyakov <abelyako@gmail.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

This long overdue trivial change to the MTD_CFI_AMDSTD kconfig menu
description is intended to help clarify that this option also supports
Spansion flash devices.
Signed-off-by: NGeorge G. Davis <gdavis@mvista.com>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

The kernel.h macro DIV_ROUND_UP performs the computation (((n) + (d) - 1) /
(d)) but is perhaps more readable.
Signed-off-by: NJulia Lawall <julia@diku.dk>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Now that we can tell when we have one of the newer DataFlash chips,
optionally expose the 128 bytes of OTP memory they provide.  Tested
on at45db642 revision B and D chips.

Switch mtdchar over to a generic HAVE_MTD_OTP flag instead of adding
another #ifdef for each type of chip whose driver has OTP support.
Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
Cc: Bryan Wu <cooloney@kernel.org>
Cc: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

The device id for Am29DL800BB in jedec_probe.c is wrong.

Reference: http://www.spansion.com/datasheets/21519c4.pdf

I discovered this while working with u-boot.

The u-boot folks mentioned Linux as an upstream reference, thought I'd
post a heads-up here too.
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

The unlock_addr rework in kernel 2.6.25 breaks 16-bit SST chips.  SST
39LF160 and SST 39VF1601 are both 16-bit only chip (do not have BYTE#
pin) and new uaddr value is not correct for them.  Add
MTD_UADDR_0xAAAA_0x5555 for those chips.  Tested with SST 39VF1601
chip.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Existing CFI driver has problems with excessive writes during erase.
If CFI driver does many writes during one erase cycle we may face the
messages with -ETIMEO error on erase operation.  It may cause the
following data corruption and kernel panics.

The reason of the issue is related to specifics of suspend operation:
if we write to flash during erase, suspend operation will cost some time
to erase procedure (for P30 it could be significant). In current version of
cfi driver the problem of many suspends is partially workarounded by adding
some time reserv to any operation (8xerase_time) but if we have many writes
during one erase the problem appears.

This patch detects the suspend and resets timer if suspend occured. It
has been well verified on different chips. No problems were found.
Could you please include the patch as it is simple and fixes bad issue.
Signed-off-by: NAlexey Korolev <akorolev@infradead.org>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Use pr_debug(...) instead of printk(KERN_DEBUG ...) so that the message
is only printed when debugging is enabled.
Signed-off-by: NJean Delvare <khali@linux-fr.org>
Tested-by: NJohn stoffel <john@stoffel.org>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

Once upon a time, the MTD repository was using CVS.

This patch therefore removes all usages of the no longer updated CVS
keywords from the MTD code.

This also includes code that printed them to the user.
Signed-off-by: NAdrian Bunk <bunk@kernel.org>
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>

This patch add support for non-CFI Eon EN29SL800B[BT] NOR flash chips.
The Eon chips have manufacturer ID in the first bank, therefore this patch
depends on support for flash chips with ID in bank other than 0.
Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>

According to JEDEC "Standard Manufacturer's Identification Code"
(http://www.jedec.org/download/search/jep106W.pdf)
several first banks of NOR flash can contain 0x7f instead of actual ID.
This patch adds support for reading manufacturer ID from banks other than 0.
Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>

Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>

Add support for M50FLW080A and M50FLW080B revisions of LPC flash
devices.
Signed-off-by: NAaron Lindner <alindner@xes-inc.com>
Signed-off-by: NNate Case <ncase@xes-inc.com>
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>

Fix typo in erase suspend while write fixup code leading to compile time 
error if CMDSET0001_DISABLE_ERASE_SUSPEND_ON_WRITE was defined.

drivers/mtd/chips/cfi_cmdset_0001.c: In function 'fixup_intel_strataflash':
drivers/mtd/chips/cfi_cmdset_0001.c:212: error: 'struct cfi_pri_amdstd' has no member named 'SuspendCmdSupport'
Signed-off-by: NAlexander Belyakov <abelyako@googlemail.com>
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>

Adding the ability to get a physical address from point() in addition
to virtual address.  This physical address is required for XIP of
userspace code from flash.
Signed-off-by: NJared Hulbert <jaredeh@gmail.com>
Reviewed-by: NJörn Engel <joern@logfs.org>
Acked-by: NNicolas Pitre <nico@cam.org>
Acked-by: NGreg Ungerer <gerg@uclinux.org>
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>

collie seems to contain LH28F640BF flash chips. According to
http://sharp-world.com/products/device/flash/pdf/*FUM00701*@E.pdf
(page 83) if they have 0x51 of Extended Query Table (number of hardware
partitions) set to zero, they have a single fixed partition.
This patch makes those chips work.
Signed-off-by: NThomas Kunze <thommycheck@gmx.de>
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>

This is a known erratum confirmed by Spansion.  I have an errata document,
but I can't find a link to it anywhere on their site to include here.

Some of the S29GL064N chips report 64 sectors when they should report 128,
and some of S29GL032N chips report 127 sectors when they should report 63.

Note that when the chip dies are fixed by Spansion, they will still have
the same id.  The fix is done in such a way that it won't affect corrected
chips.

The fixups use the extended id made available by a previous patch.  Without
that, virtually all newer AMD/Spansion chips will have the same ID (0x227e)
and it's not possible to apply the fixup to the correct chips.
Signed-off-by: NTrent Piepho <tpiepho@freescale.com>
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>

AMD/Spansion use a device id of 0x7e to indicate an extended device is
present at offset 0xe and 0xf in the query data.

I've verified with Spansion that all their chips (mfr == 0x01) with an id
of 0x7e use it to indicate an extended id is present.  What's more, there
are no chips with a NON-extended id that is the same as a different chip's
extended id.  In other words, when the extended ID is present, one can
replace the normal id with the extended id without losing any information.
Which is what I've done.
Signed-off-by: NTrent Piepho <tpiepho@freescale.com>
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>

Add support for the SST 36VF3203 flash chip. It is used on Emerson 
KSI8560 board.
Signed-off-by: NAndrei Dolnikov <adolnikov@ru.mvista.com>
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>

Untested, but shouldn't break anything... Makes MTD_XIP arch
independent. I guess this is why xip_iprefetch() was made for.
Signed-off-by: NPaulius Zaleckas <paulius.zaleckas@teltonika.lt>
Acked-by: NNicolas Pitre <nico@cam.org>
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>

This patch makes the needlessly global cfi_staa_erase_varsize() static.
Signed-off-by: NAdrian Bunk <bunk@kernel.org>
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>

__FUNCTION__ is gcc-specific, use __func__
Signed-off-by: NHarvey Harrison <harvey.harrison@gmail.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>