Add context save and restore for CORE powerdomain resources in order
to support off-mode.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Adds a 'save_state' option when calling into SRAM idle function
and adds some minor cleanups of SRAM asm code.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

During the MMU restoration on the restore path from MPU OFF, the page
table entry for the page consisting of the code being executed is
modified to make MMU return VA=PA.

The MMU is then enabled and the original entry is being stored in
scratchpad.  This patch reads the original values stored in
scratchpad, and restores them back.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Expand the powerdomains handled in the idle path to include PER, NEON
and CORE.  This includes properly clearing the previous powerstates,
linking NEON state to MPU state and calling the UART prepare functions
for only the appropraite powerdomain transitions (CORE for UART1,2,
PER for UART3.)
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Generalize the copy of SRAM functions into omap_push_sram_idle()
so it can be used on init but also after off-mode transitions.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Add context save and restore for the System Control Module to suport
off-mode.

ETK and debobs definitions added by Peter De Schrijver.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NPeter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch populates the scratchpad contents as expected by the
bootROM code.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Add context save and restore for PRCM module to support off-mode.
Additional registers (CM_CLKSEL4, CM_CLKEN, CM_CLKEN2) added by Tero
Kristo.

Missing CM_CLKEN_PLL_IVA2 register added by Kalle Jokiniemi.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NTero Kristo <tero.kristo@nokia.com>
Signed-off-by: NKalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Add context save and restore for the INTC module to support off-mode.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Add context save and restore to enable off-mode.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch adds the context save and restore functions for GPMC to
enable off-mode.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

cpu_is_xxx() macros are identifying generic at91sam9g45 chip. This patch adds
the capacity to differentiate Engineering Samples and final lots through the
inclusion of  at91_cpu_fully_identify() and the related chip IDs with chip
version field preserved.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NHans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>

Somme common drivers will need those at91 cpu_is_xxx() definitions. As
at91sam9g10 and at91sam9g45 are on the way to linus' tree, here is the patch
that adds those chips to cpu.h in AVR32 architecture.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NHaavard Skinnemoen <haavard.skinnemoen@atmel.com>

This reverts commit b94b0808.

genksyms currently cannot handle complicated types for exported
percpu variables.  Drop this patch for now as it prevents a
module from being loaded on sn2 systems:

 xpc: no symbol version for per_cpu____sn_cnodeid_to_nasid
 xpc: Unknown symbol per_cpu____sn_cnodeid_to_nasid
Signed-off-by: NTony Luck <tony.luck@intel.com>

Mapping the same memory using two different attributes (memory
type, shareability, cacheability) is unpredictable.  During boot,
we encounter a situation when we're updating the kernel's page
tables which can lead to dirty cache lines existing in the cache
which are subsequently missed.  This causes stack corruption,
and therefore a crash.

Therefore, ensure that the shared and cacheability settings
matches the configuration that will be used later; this together
with the restriction in early_cachepolicy() ensures that we won't
create a mismatch during boot.
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

ARM unwind is known to compile only with EABI and not-buggy compilers.
The problem is not the unwinding information but the -fno-frame-pointer
option added as a result of !CONFIG_FRAME_POINTER.  Now we check the
compiler and raise a #warning in case of wrong compiler.
Signed-off-by: NClaudio Scordino <claudio@evidence.eu.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

sys_ppoll syscall needs to use a compat handler on 64bit kernels with o32
user-space.
Signed-off-by: NArnaud Patard <apatard@mandriva.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Unify the naming method between kernel and the user-space oprofile tool.
Because loongson is used instead of godson in most of the places, we agreed
to use loongson instead, which will simplify future maintenance.
Signed-off-by: NWu Zhangjin <wuzhangjin@gmail.com>
Acked-by: NRobert Richter <robert.richter@amd.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The handle_edge_irq() flowhandler disables edge int sources which occur
too fast (i.e. another edge comes in before the irq handler function
had a chance to finish).  Currently, the mask_ack() callback does not
ack the edges in hardware, leading to an endless loop in the flowhandler
where it tries to shut up the irq source.

When I rewrote the alchemy IRQ code  I wrongly assumed the mask_ack()
callback was only used by the level flowhandler, hence it omitted the
(at the time pointless) edge acks.  Turned out I was wrong; so here
is a complete mask_ack implementation for Alchemy IC, which fixes
the above mentioned problem.
Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

TXx9 SPI bit rate is calculated by:
	fBR = fSPI / 2 / (n + 1)
	(fSPI is SPI master clock freq, i.e. imbusclk freq.)
So use imbus_clk / 2 as a spi-baseclk.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

For consistency with other BCM63xx SoC set the CPU name to "Broadcom
BCM6338" when actually running on that system.
Signed-off-by: NFlorian Fainelli <florian@openwrt.org>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Loongson 2 does not have dcache aliases when is using 16k pages. and the

And because Loongson 2 doesn't do SMP , cpu_icache_snoops_remote_store does
not matter here.
Signed-off-by: NZhang Le <r0bertz@gentoo.org>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

set_saved_sp reads Context register. Avoid reading stale value from
earlier incomplete write.

Issue found and fixed for head.S by Chris Dearman <chris@mips.com>.
Signed-off-by: NChris Dearman <chris@mips.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Some newer Octeon chips have registers that allow lockless operation of
the interrupt controller.  Take advantage of them.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Since the locks are used from interrupt context we need the
irqsave/irqrestore versions of the locking functions.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NChris Dearman <chris@mips.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NChris Dearman <chris@mips.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NChris Dearman <chris@mips.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: Chris Dearman (chris@mips.com)
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This patch ensures that the sign bit is always updated for NaN operands.
Signed-off-by: NChris Dearman <chris@mips.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NChris Dearman <chris@mips.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Based on original patch by Chris Dearman <chris@mips.com>.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This fixes the remaining problems introduced by
f1974653 (incorrect access length &
byteswapping in bigendian mode)
Signed-off-by: NChris Dearman <chris@mips.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

On an SMP system with cache aliases, the following sequence of events may
happen:

1) copy_user_highpage() runs on CPU0, invoking kmap_coherent() to create a
   temporary mapping in the fixmap region
2) copy_page() starts on CPU0
3) CPU1 sends CPU0 an IPI asking CPU0 to run local_r4k_flush_cache_page()
4) CPU0 takes the interrupt, interrupting copy_page()
5) local_r4k_flush_cache_page() on CPU0 calls kmap_coherent() again
6) The second invocation of kmap_coherent() on CPU0 tries to use the
   same fixmap virtual address that was being used by copy_user_highpage()
7) CPU0 throws a machine check exception for the TLB address conflict

Fixed by creating an extra set of fixmap entries for use in interrupt
handlers.  This prevents fixmap VA conflicts between copy_user_highpage()
running in user context, and local_r4k_flush_cache_page() invoked from an
SMP IPI.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This patch checks if the watchdog enable bit is set in the DCL register
meaning that the hardware watchdog actually works and if so, register the
ar7_wdt platform_device.
Signed-off-by: NFlorian Fainelli <florian@openwrt.org>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This patch prepares the board code to register a bcm63xx_wdt
platform_device that we are going to use in a subsequent patch.
Signed-off-by: NFlorian Fainelli <florian@openwrt.org>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>