1. 23 3月, 2011 1 次提交
    • C
      drm/i915: Disable pagefaults along execbuffer relocation fast path · d4aeee77
      Chris Wilson 提交于
      Along the fast path for relocation handling, we attempt to copy directly
      from the user data structures whilst holding our mutex. This causes
      lockdep to warn about circular lock dependencies if we need to pagefault
      the user pages. [Since when handling a page fault on a mmapped bo, we
      need to acquire the struct mutex whilst already holding the mm
      semaphore, it is then verboten to acquire the mm semaphore when already
      holding the struct mutex. The likelihood of the user passing in the
      relocations contained in a GTT mmaped bo is low, but conceivable for
      extreme pathology.] In order to force the mm to return EFAULT rather
      than handle the pagefault, we therefore need to disable pagefaults
      across the relocation fast path.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: stable@kernel.org
      Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      d4aeee77
  2. 07 3月, 2011 2 次提交
  3. 02 3月, 2011 2 次提交
  4. 22 2月, 2011 3 次提交
    • C
      drm/i915: Use a device flag for non-interruptible phases · ce453d81
      Chris Wilson 提交于
      The code paths for modesetting are growing in complexity as we may need
      to move the buffers around in order to fit the scanout in the aperture.
      Therefore we face a choice as to whether to thread the interruptible status
      through the entire pinning and unbinding code paths or to add a flag to
      the device when we may not be interrupted by a signal. This does the
      latter and so fixes a few instances of modesetting failures under stress.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      ce453d81
    • C
      drm/i915: First try a normal large kmalloc for the temporary exec buffers · 8408c282
      Chris Wilson 提交于
      As we just need a temporary array whilst performing the relocations for
      the execbuffer, first attempt to allocate using kmalloc even if it is
      not of order page-0. This avoids the overhead of remapping the
      discontiguous array and so gives a moderate boost to execution
      throughput.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      8408c282
    • C
      drm/i915: Protect against drm_gem_object not being the first member · c8725226
      Chris Wilson 提交于
      Dave Airlie spotted that we had a potential bug should we ever rearrange
      the drm_i915_gem_object so not the base drm_gem_object was not its first
      member. He noticed that we often convert the return of
      drm_gem_object_lookup() immediately into drm_i915_gem_object and then
      check the result for nullity. This is only valid when the base object is
      the first member and so the superobject has the same address. Play safe
      instead and use the compiler to convert back to the original return
      address for sanity testing.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      c8725226
  5. 07 2月, 2011 1 次提交
  6. 23 1月, 2011 1 次提交
  7. 19 1月, 2011 1 次提交
  8. 14 1月, 2011 3 次提交
  9. 12 1月, 2011 5 次提交
  10. 20 12月, 2010 1 次提交
  11. 10 12月, 2010 2 次提交
  12. 06 12月, 2010 1 次提交
  13. 05 12月, 2010 1 次提交
  14. 02 12月, 2010 2 次提交
    • C
      drm/i915: Pipelined fencing [infrastructure] · d9e86c0e
      Chris Wilson 提交于
      With this change, every batchbuffer can use all available fences (save
      pinned and scanout, of course) without ever stalling the gpu!
      
      In theory. Currently the actual pipelined update of the register is
      disabled due to some stability issues. However, just the deferred update
      is a significant win.
      
      Based on a series of patches by Daniel Vetter.
      
      The premise is that before every access to a buffer through the GTT we
      have to declare whether we need a register or not. If the access is by
      the GPU, a pipelined update to the register is made via the ringbuffer,
      and we track the last seqno of the batches that access it. If by the
      CPU we wait for the last GPU access and update the register (either
      to clear or to set it for the current buffer).
      
      One advantage of being able to pipeline changes is that we can defer the
      actual updating of the fence register until we first need to access the
      object through the GTT, i.e. we can eliminate the stall on set_tiling.
      This is important as the userspace bo cache does not track the tiling
      status of active buffers which generate frequent stalls on gen3 when
      enabling tiling for an already bound buffer.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      d9e86c0e
    • C
  15. 30 11月, 2010 1 次提交
  16. 28 11月, 2010 1 次提交
  17. 26 11月, 2010 2 次提交