1. 23 11月, 2012 2 次提交
    • T
      dma: mv_xor: use request_irq() instead of devm_request_irq() · 2d0a0745
      Thomas Petazzoni 提交于
      Even through the usage of devm_*() functions is generally recommended
      over their classic variants, in the case of devm_request_irq()
      combined with irq_of_parse_and_map(), it doesn't work nicely.
      
      We have the following scenario:
      
       irq_of_parse_and_map(...)
       devm_request_irq(...)
      
      For some reason, the driver initialization fails at a later
      point. Since irq_of_parse_and_map() is no device-managed, we do a:
      
       irq_dispose_mapping(...)
      
      Unfortunately, this doesn't work, because the free_irq() must be done
      prior to calling irq_dispose_mapping(). But with the devm mechanism,
      the automatic free_irq() would happen only after we get out of the
      ->probe() function.
      
      So basically, we revert to using request_irq() with traditional error
      handling, so that in case of error, free_irq() gets called before
      irq_dispose_mapping().
      Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
      2d0a0745
    • T
      dma: mv_xor: clear the window override control registers · c4b4b732
      Thomas Petazzoni 提交于
      The XOR channels on Marvell SoCs have a Window Override Control
      register that allow to do some fancy things with addresses. Those
      features are not used by the driver, but some U-Boot versions anyway
      modify those registers.
      
      For some reason, the U-Boot on OpenBlocks AX3-4 was setting an invalid
      value in those registers when the addition 2 GB DRAM chip was plugged
      into the board, causing the XOR driver to fail in using the XOR
      engines.
      
      By setting those registers to 0 during the driver initialization, we
      ensure that the registers are configured according with the driver
      operation model.
      
      Thanks to Lior Amsalem <alior@marvell.com> for his help in debugging
      this problem.
      Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
      c4b4b732
  2. 21 11月, 2012 5 次提交
  3. 20 11月, 2012 31 次提交
  4. 17 11月, 2012 1 次提交
  5. 16 11月, 2012 1 次提交
    • T
      net: mvneta: driver for Marvell Armada 370/XP network unit · c5aff182
      Thomas Petazzoni 提交于
      This patch contains a new network driver for the network unit of the
      ARM Marvell Armada 370 and the Armada XP. Both SoCs use the PJ4B
      processor, a Marvell-developed ARM core that implements the ARMv7
      instruction set.
      
      Compared to previous ARM Marvell SoCs (Kirkwood, Orion, Discovery),
      the network unit in Armada 370 and Armada XP is highly different. This
      is the reason why this new 'mvneta' driver is needed, while the older
      ARM Marvell SoCs use the 'mv643xx_eth' driver.
      
      Here is an overview of the most important hardware changes that
      require a new, specific, driver for the network unit of Armada 370/XP:
      
       - The new network unit has a completely different design and layout
         for the RX and TX descriptors. They are now organized as a simple
         array (each RX and TX queue has base address and size of this
         array) rather than a linked list as in the old SoCs.
      
       - The new network unit has a different RXQ and TXQ management: this
         management is done using special read/write counter registers,
         while in the Old SocS, it was done using the Ownership bit in RX
         and TX descriptors.
      
       - The new network unit has different interrupt registers
      
       - The new network unit way of cleaning of interrupts is not done by
         writing to the cause register, but by updating per-queue counters
      
       - The new network unit has different GMAC registers (link, speed,
         duplex configuration) and different WRR registers.
      
       - The new network unit has lots of new units like PnC (Parser and
         Classifier), PMT, BM (Memory Buffer Management), xPON, and more.
      
      The driver proposed in the current patch only handles the basic
      features. Additional hardware features will progressively be supported
      as needed.
      
      This code has originally been written by Rami Rosen
      <rosenr@marvell.com>, and then reviewed and cleaned up by Thomas
      Petazzoni <thomas.petazzoni@free-electrons.com>.
      Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
      Acked-by: NDavid S. Miller <davem@davemloft.net>
      c5aff182