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  1. 25 12月, 2011 1 次提交
  3. 30 8月, 2011 1 次提交
  5. 26 8月, 2011 2 次提交
  7. 25 8月, 2011 1 次提交
  9. 24 8月, 2011 1 次提交
  11. 18 8月, 2011 1 次提交
  13. 12 8月, 2011 2 次提交
  15. 05 8月, 2011 1 次提交
  17. 04 8月, 2011 1 次提交
    • L
      mrst_pmu: driver for Intel Moorestown Power Management Unit · 6dccf9c5
      由 Len Brown 提交于 
      The Moorestown (MRST) Power Management Unit (PMU) driver
directs the SOC power states in the "Langwell" south complex (SCU).

It hooks pci_platform_pm_ops[] and thus observes all PCI ".set_state"
requests.  For devices in the SC, the pmu driver translates those
PCI requests into the appropriate commands for the SCU.

The PMU driver helps implement S0i3, a deep system idle power idle state.
Entry into S0i3 is via cpuidle, just like regular processor c-states.
S0i3 depends on pre-conditions including uni-processor, graphics off,
and certain IO devices in the SC must be off.  If those pre-conditions
are met, then the PMU allows cpuidle to enter S0i3, otherwise such requests
are demoted, either to Atom C4 or Atom C6.

This driver is based on prototype work by Bruce Flemming,
Illyas Mansoor, Rajeev D. Muralidhar, Vishwesh M. Rudramuni,
Hari Seshadri and Sujith Thomas.  The current driver also
includes contributions from H. Peter Anvin, Arjan van de Ven,
Kristen Accardi, and Yong Wang.

Thanks for additional review feedback from Alan Cox and Randy Dunlap.
Acked-by: NAlan Cox <alan@linux.intel.com>
Acked-by: NH. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: NLen Brown <len.brown@intel.com>
      6dccf9c5
  19. 03 8月, 2011 1 次提交
  21. 02 8月, 2011 1 次提交
  23. 01 8月, 2011 1 次提交
  25. 30 7月, 2011 1 次提交
    • D
      cpupowerutils - cpufrequtils extended with quite some features · 7fe2f639
      由 Dominik Brodowski 提交于 
      CPU power consumption vs performance tuning is no longer
limited to CPU frequency switching anymore: deep sleep states,
traditional dynamic frequency scaling and hidden turbo/boost
frequencies are tied close together and depend on each other.
The first two exist on different architectures like PPC, Itanium and
ARM, the latter (so far) only on X86. On X86 the APU (CPU+GPU) will
only run most efficiently if CPU and GPU has proper power management
in place.

Users and Developers want to have *one* tool to get an overview what
their system supports and to monitor and debug CPU power management
in detail. The tool should compile and work on as many architectures
as possible.

Once this tool stabilizes a bit, it is intended to replace the
Intel-specific tools in tools/power/x86
Signed-off-by: NDominik Brodowski <linux@dominikbrodowski.net>
      7fe2f639
  27. 29 7月, 2011 2 次提交
  29. 28 7月, 2011 2 次提交
  31. 26 7月, 2011 2 次提交
  33. 23 7月, 2011 2 次提交
    • M
      regmap: Add generic non-memory mapped register access API · b83a313b
      由 Mark Brown 提交于 
      There are many places in the tree where we implement register access for
devices on non-memory mapped buses, especially I2C and SPI. Since hardware
designers seem to have settled on a relatively consistent set of register
interfaces this can be effectively factored out into shared code.  There
are a standard set of formats for marshalling data for exchange with the
device, with the actual I/O mechanisms generally being simple byte
streams.

We create an abstraction for marshaling data into formats which can be
sent on the control interfaces, and create a standard method for
plugging in actual transport underneath that.

This is mostly a refactoring and renaming of the bottom level of the
existing code for sharing register I/O which we have in ASoC. A
subsequent patch in this series converts ASoC to use this.  The main
difference in interface is that reads return values by writing to a
location provided by a pointer rather than in the return value, ensuring
we can use the full range of the type for register data.  We also use
unsigned types rather than ints for the same reason.

As some of the devices can have very large register maps the existing
ASoC code also contains infrastructure for managing register caches.
This cache work will be moved over in a future stage to allow for
separate review, the current patch only deals with the physical I/O.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@ti.com>
Acked-by: NGreg Kroah-Hartman <gregkh@suse.de>
Acked-by: NWolfram Sang <w.sang@pengutronix.de>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
      b83a313b
    • J
      OpenRISC: Add MAINTAINERS entry · 19f9d392
      由 Jonas Bonn 提交于 
      Signed-off-by: NJonas Bonn <jonas@southpole.se>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
      19f9d392
  35. 22 7月, 2011 1 次提交
  37. 21 7月, 2011 3 次提交
  39. 19 7月, 2011 1 次提交
  41. 16 7月, 2011 1 次提交
  43. 14 7月, 2011 1 次提交
  45. 13 7月, 2011 1 次提交
  47. 12 7月, 2011 1 次提交
  49. 09 7月, 2011 1 次提交
  51. 07 7月, 2011 2 次提交
  53. 06 7月, 2011 5 次提交