提交 · 2c22d8baa98a92022acb85b0b7c6f4a60df55f47 · openeuler / raspberrypi-kernel

07 12月, 2006 40 次提交

[PATCH] relocatable kernel: Fix kallsyms on avr32 after relocatable kernel changes · 2c22d8ba

由 Vivek Goyal 提交于 12月 07, 2006

o On some platforms like avr32, section init comes before .text and
  not necessarily a symbol's relative position w.r.t _text is positive.
  In such cases assembler detects the overflow and emits warning. This
  patch fixes it.
Signed-off-by: NVivek Goyal <vgoyal@in.ibm.com>
Signed-off-by: NAndi Kleen <ak@suse.de>
Cc: Andi Kleen <ak@suse.de>
Cc: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>

2c22d8ba

[PATCH] i386: alloc_gdt() static · ba10650a

由 Adrian Bunk 提交于 12月 07, 2006

Make the needlessly global alloc_gdt() static.

(against) pda-percpu-init
Signed-off-by: NAdrian Bunk <bunk@stusta.de>
Signed-off-by: NAndi Kleen <ak@suse.de>
Cc: Andi Kleen <ak@muc.de>
Cc: Jeremy Fitzhardinge <jeremy@goop.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>

ba10650a

[PATCH] i386: fix MTRR code · 365bff80

由 Jan Beulich 提交于 12月 07, 2006

Until not so long ago, there were system log messages pointing to
inconsistent MTRR setup of the video frame buffer caused by the way vesafb
and X worked. While vesafb was fixed meanwhile, I believe fixing it there
only hides a shortcoming in the MTRR code itself, in that that code is not
symmetric with respect to the ordering of attempts to set up two (or more)
regions where one contains the other. In the current shape, it permits
only setting up sub-regions of pre-exisiting ones. The patch below makes
this symmetric.

While working on that I noticed a few more inconsistencies in that code,
namely
- use of 'unsigned int' for sizes in many, but not all places (the patch
  is converting this to use 'unsigned long' everywhere, which specifically
  might be necessary for x86-64 once a processor supporting more than 44
  physical address bits would become available)
- the code to correct inconsistent settings during secondary processor
  startup tried (if necessary) to correct, among other things, the value
  in IA32_MTRR_DEF_TYPE, however the newly computed value would never get
  used (i.e. stored in the respective MSR)
- the generic range validation code checked that the end of the
  to-be-added range would be above 1MB; the value checked should have been
  the start of the range
- when contained regions are detected, previously this was allowed only
  when the old region was uncacheable; this can be symmetric (i.e. the new
  region can also be uncacheable) and even further as per Intel's
  documentation write-trough and write-back for either region is also
  compatible with the respective opposite in the other
Signed-off-by: NJan Beulich <jbeulich@novell.com>
Signed-off-by: NAndi Kleen <ak@suse.de>

365bff80

[PATCH] x86-64: adjust pmd_bad() · eab724e5

由 Jan Beulich 提交于 12月 07, 2006

Make pmd_bad() symmetrical to pgd_bad() and pud_bad(). At once,
simplify them all.

TBD: tighten down the checks again as suggested by Hugh D.
Signed-off-by: NJan Beulich <jbeulich@novell.com>
Signed-off-by: NAndi Kleen <ak@suse.de>

eab724e5

[PATCH] i386: conditionalize inclusion of some MTRR flavors · 475850c8

由 Jan Beulich 提交于 12月 07, 2006

Avoid inclusion of code that's dead for x86-64.
Signed-off-by: NJan Beulich <jbeulich@novell.com>
Signed-off-by: NAndi Kleen <ak@suse.de>

475850c8

[PATCH] x86-64: remove prototype of free_bootmem_generic() · 4a1c4227

由 Jan Beulich 提交于 12月 07, 2006

The function doesn't exist (anymore).
Signed-off-by: NJan Beulich <jbeulich@novell.com>
Signed-off-by: NAndi Kleen <ak@suse.de>

4a1c4227

[PATCH] i386: Don't touch per cpu memory of offline CPUs in touch_nmi_watchdog · c6ea396d

由 Jan Beulich 提交于 12月 07, 2006

Just like on x86-64, don't touch foreign CPUs' memory if the watchdog
isn't enabled at all.
Signed-off-by: NJan Beulich <jbeulich@novell.com>
Signed-off-by: NAndi Kleen <ak@suse.de>

c6ea396d

[PATCH] i386: clear_fixmap() should not use set_pte() · b0bfece4

由 Jan Beulich 提交于 12月 07, 2006

While not strictly required with the current code (as the upper half of
page table entries generated by __set_fixmap() cannot be non-zero due
to the second parameter of this function being 'unsigned long'), the
use of set_pte() in __set_fixmap() in the context of clear_fixmap() is
still improper with CONFIG_X86_PAE (see the respective comment in
include/asm-i386/pgtable-3level.h) and would turn into a bug if that
second parameter ever gets changed to a 64-bit type.
Signed-off-by: NJan Beulich <jbeulich@novell.com>
Signed-off-by: NAndi Kleen <ak@suse.de>

b0bfece4

A
[PATCH] x86-64: Rate limit no irq handler messages · 9a457324
由 Andi Kleen 提交于 12月 07, 2006
```
Signed-off-by: NAndi Kleen <ak@suse.de>
```
9a457324

[PATCH] x86-64: fix perms/range of vsyscall vma in /proc/*/maps · 103efcd9

由 Ernie Petrides 提交于 12月 07, 2006

The final line of /proc/<pid>/maps on x86_64 for native 64-bit
tasks shows an incorrect ending address and incorrect permissions.  There
is only a single page mapped in this vsyscall region, and it is accessible
for both read and execute.

The patch below fixes this.  (Since 32-bit-compat tasks have a real vma
with correct perms/range, no change is necessary for that scenario.)

Before the patch, a "cat /proc/self/maps | tail -1" shows this:

        ffffffffff600000-ffffffffffe00000 ---p 00000000 [...]

After the patch, this is the output:

        ffffffffff600000-ffffffffff601000 r-xp 00000000 [...]
Signed-off-by: NErnie Petrides <petrides@redhat.com>
Signed-off-by: NAndi Kleen <ak@suse.de>

103efcd9

[PATCH] i386: Add support for compilation for Core2 · c55d92d1

由 Andi Kleen 提交于 12月 07, 2006

gcc doesn't support -mtune=core2 yet, but will be soon. Use -mtune=generic or -mtune=i686
as fallback

TBD need benchmarking for INTEL_USERCOPY etc. So far I used the same defaults as MPENTIUMM
Signed-off-by: NAndi Kleen <ak@suse.de>

c55d92d1

[PATCH] x86-64: Add option to compile for Core2 · 71381998

由 Andi Kleen 提交于 12月 07, 2006

Add an option to compile for Intel's Core 2

The Kconfig help is a mouthful due to the inventiveness of Intel's
product naming department.

Mainly for the 64bit cache line sizes because gcc doesn't support
optimizing for core2 yet. However it will and then the kernel
should be ready by passing the right option

Also fix the old MPSC help text to confirm better to reality.
Signed-off-by: NAndi Kleen <ak@suse.de>

71381998

[PATCH] paravirt: Add option to allow skipping the timer check · 8542b200

由 Zachary Amsden 提交于 12月 07, 2006

Add a way to disable the timer IRQ routing check via a boot option.  The
VMI timer code uses this to avoid triggering the pester Mingo code, which
probes for some very unusual and broken motherboard routings.  It fires
100% of the time when using a paravirtual delay mechanism instead of using
a realtime delay, since there is no elapsed real time, and the 4 timer IRQs
have not yet been delivered.

In addition, it is entirely possible, though improbable, that this bug
could surface on real hardware which picks a particularly bad time to enter
SMM mode, causing a long latency during one of the timer IRQs.

While here, make check_timer be __init.
Signed-off-by: NZachary Amsden <zach@vmware.com>
Signed-off-by: NAndi Kleen <ak@suse.de>
[chrisw: use no_timer_check to bring inline with x86_64 as per Andi's request]
Signed-off-by: NChris Wright <chrisw@sous-sol.org>
Cc: Andi Kleen <ak@suse.de>
Signed-off-by: NAndrew Morton <akpm@osdl.org>

8542b200

[PATCH] paravirt: fix missing pte update · 8ecb8950

由 Zachary Amsden 提交于 12月 07, 2006

The function ptep_get_and_clear uses an atomic instruction sequence to get and
clear an active pte.  Rather than add such an atomic operator to all virtual
machine implementations in paravirt-ops, it is easier to support the raw
atomic sequence and use either a trapping writable pagetable approach, or a
post-update notification.  For the post update notification, we require the
pte_update function to be called after the access.  Combine the 2-level and
3-level paging operators into one common function which does the post-update
notification, and rename the actual atomic sequences to raw_ptep_xxx
operators.
Signed-off-by: NZachary Amsden <zach@vmware.com>
Signed-off-by: NAndi Kleen <ak@suse.de>
Cc: Andi Kleen <ak@muc.de>
Cc: Jeremy Fitzhardinge <jeremy@goop.org>
Cc: Chris Wright <chrisw@sous-sol.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>

8ecb8950

[PATCH] paravirt: fix parameter names in mmu operations · dfbea0ad

由 Zachary Amsden 提交于 12月 07, 2006

Make parameter names match function argument names for the yet to be defined
pte_update_defer accessor.
Signed-off-by: NZachary Amsden <zach@vmware.com>
Signed-off-by: NAndi Kleen <ak@suse.de>
Cc: Andi Kleen <ak@muc.de>
Cc: Jeremy Fitzhardinge <jeremy@goop.org>
Cc: Chris Wright <chrisw@sous-sol.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>

dfbea0ad

[PATCH] paravirt: Preparatory mmu header movement · a2952d89

由 Zachary Amsden 提交于 12月 07, 2006

Move header includes for the nopud / nopmd types to the location of the actual
pte / pgd type definitions.  This allows generic 4-level page type code to be
written before the split 2/3 level page table headers are included.
Signed-off-by: NZachary Amsden <zach@vmware.com>
Signed-off-by: NAndi Kleen <ak@suse.de>
Cc: Andi Kleen <ak@muc.de>
Cc: Jeremy Fitzhardinge <jeremy@goop.org>
Cc: Chris Wright <chrisw@sous-sol.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>

a2952d89

[PATCH] paravirt: Be careful about touching BIOS address space · bd472c79