- 21 6月, 2012 4 次提交
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由 Andy Shevchenko 提交于
In case the first descriptor we found is available, the counter still remains 0 value which is wrong. This patch fixes the counter behaviour. Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: NViresh Kumar <viresh.linux@gmail.com> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Andy Shevchenko 提交于
There is three places where values of the most significant registers were printed. Make such piece of code as separate function. Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: NViresh Kumar <viresh.linux@gmail.com> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Andy Shevchenko 提交于
dma_addr_t is sometimes 32 bit and sometimes 64. We normally cast them to unsigned long long for printk(). Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: NViresh Kumar <viresh.linux@gmail.com> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Andy Shevchenko 提交于
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: NViresh Kumar <viresh.linux@gmail.com> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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- 20 6月, 2012 1 次提交
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由 Zhangfei Gao 提交于
Add support for two-channel dma under dmaengine support: mmp-adma and pxa910-squ Signed-off-by: NZhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: NLeo Yan <leoy@marvell.com> Signed-off-by: NQiao Zhou <zhouqiao@marvell.com> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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- 14 6月, 2012 2 次提交
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由 Linus Walleij 提交于
Allocate memory, region, remap and irq for device state using devm_* helpers to simplify memory accounting. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Javi Merino 提交于
pl330_update() stores a pointer to the thrd->req that finished, which contains a pointer to the corresponding pl330_req. This is done with the pl330_lock held. Then, it iterates through the req_done list, calling the callback for each of the requests that are done. The problem is that the driver releases the lock before calling the callback for each of the callbacks. pl330_submit_req() running in another processor can then acquire the lock and insert another request in one of the thrd->req that hasn't been processed yet, replacing the pointer to pl330_req there. When the callback returns in pl330_update() and the next rqdone is popped from the list, it dereferences the pl330_req pointer to the just scheduled pl330_req, instead of the one that has finished, calling pl330 with the wrong r. This patch fixes this by storing the pointer to pl330_req directly in the list. Signed-off-by: NJavi Merino <javi.merino@arm.com> Cc: Jassi Brar <jaswinder.singh@linaro.org> Acked-by: NJassi Brar <jaswinder.singh@linaro.org> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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- 12 6月, 2012 1 次提交
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由 Nicolas Ferre 提交于
Not all Atmel SoCs were pointed out in header comment which was bringing confusion. Remove the truncated list of supported devices, replace by the only one that is not supported. Reported-by: NElen Song <elen.song@atmel.com> Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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- 08 6月, 2012 1 次提交
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由 Laxman Dewangan 提交于
Add dmaengine based NVIDIA's Tegra APB DMA driver. This driver support the slave mode of data transfer from peripheral to memory and vice versa. The driver supports for the cyclic and non-cyclic mode of data transfer. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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- 07 6月, 2012 4 次提交
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由 Huang Shijie 提交于
enable the mxs-dma for imx6q. Also remove the unused header file. Signed-off-by: NHuang Shijie <shijie8@gmail.com> Acked-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Sachin Kamat 提交于
Fixes the following sparse warning: drivers/dma/pl330.c:2542:5: warning: symbol 'add_desc' was not declared. Should it be static? Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Richard Zhao 提交于
This fix audio underrun issue. When SNDRV_PCM_TRIGGER_STOP and SNDRV_PCM_TRIGGER_START, it calls prepare again. buf_tail should be reset to zero. So move buf_tail initialization into prepare function. Signed-off-by: NRichard Zhao <richard.zhao@freescale.com> Acked-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Tushar Behera 提交于
Commit eab21585 ("dmaengine: pl330: dont complete descriptor for cyclic dma") wrongly completes descriptor for cyclic dma, hence following BUG_ON is still hit with cyclic DMA operations. kernel BUG at drivers/dma/dmaengine.h:53! Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Acked-by: NJassi Brar <jaswinder.singh@linaro.org> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com> Cc: stable <stable@vger.kernel.org>
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- 15 5月, 2012 3 次提交
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由 Nicolas Ferre 提交于
The maxburst/chunk size was taken from the private slave DMA data structure. Use the common API provided by DMA_SLAVE_CONFIG to setup src/dst maxburst values. The ctrla field is not needed anymore in the slave private structure nor the header constants that were located in an architecture specific directory. The at91sam9g45_devices.c file that was using this platform data is also modified to remove this now useless data. Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Nicolas Ferre 提交于
Not needed constant that was set to 0. Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Vinod Koul 提交于
for cyclic dma, dont makr the descriptor as complte. Fix the remaining users of cyclic dma which do so Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com> Tested-by: NNicolas Ferre <nicolas.ferre@atmel.com> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com> Tested-by: NMika Westerberg <mika.westerberg@iki.fi>
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- 12 5月, 2012 4 次提交
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由 Dong Aisheng 提交于
Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Rob Landley <rob@landley.net> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Huang Shijie <b32955@freescale.com> Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org> Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NMarek Vasut <marex@denx.de> Acked-by: NVinod Koul <vinod.koul@intel.com>
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由 Shawn Guo 提交于
Rewrite mxs_dma_is_apbh and mxs_dma_is_apbx in order to support other SoCs like imx6q and reform the platform_device_id for the better further dt support. Cc: Dan Williams <dan.j.williams@intel.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Huang Shijie <b32955@freescale.com> Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org> Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NMarek Vasut <marex@denx.de> Acked-by: NVinod Koul <vinod.koul@intel.com>
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由 Shawn Guo 提交于
Let macros dma_is_apbh and apbh_is_old take mxs_dma as parameter to make the code easy to read. Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Dong Aisheng 提交于
This can get rid of the mach-dependency. Cc: Dan Williams <dan.j.williams@intel.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Huang Shijie <b32955@freescale.com> Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org> Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NWolfram Sang <w.sang@pengutronix.de> Acked-by: NMarek Vasut <marex@denx.de> Acked-by: NVinod Koul <vinod.koul@intel.com>
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- 11 5月, 2012 8 次提交
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由 Richard Zhao 提交于
device_prep_dma_cyclic may be call in audio trigger function which is atomic context, so we make it atomic too. - change channel0 lock to spinlock. - Use polling to wait for channel0 finish running. Signed-off-by: NRichard Zhao <richard.zhao@freescale.com> Acked-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Lars-Peter Clausen 提交于
sg->length may or may not contain the length of the dma region to transfer, depending on the architecture - dma_sg_len(sg) always will though. For the architectures which use the drivers modified by this patch it probably is the case that sg->length contains the dma transfer length. But to be consistent and future proof change them to use dma_sg_len. To quote Russel King: sg->length is meaningless to something performing DMA. In cases where sg_dma_len(sg) and sg->length are the same storage, then there's no problem. But scatterlists _can_ (and one some architectures) do split them - especially when you have an IOMMU which can allow you to combine a scatterlist into fewer entries. So, anything using sg->length for the size of a scatterlist's DMA transfer _after_ a call to dma_map_sg() is almost certainly buggy. The patch has been generated using the following coccinelle patch: <smpl> @@ struct scatterlist *sg; expression X; @@ -sg[X].length +sg_dma_len(&sg[X]) @@ struct scatterlist *sg; @@ -sg->length +sg_dma_len(sg) </smpl> Signed-off-by: NLars-Peter Clausen <lars@metafoo.de> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Lars-Peter Clausen 提交于
dmaengine drivers should always use sg_dma_address instead of sg_phys to get the addresses for the transfer from a sg element. To quote Russel King: sg_phys(sg) of course has nothing to do with DMA addresses. It's the physical address _to the CPU_ of the memory associated with the scatterlist entry. That may, or may not have the same value for the DMA engine, particularly if IOMMUs are involved. And if these drivers are used on ARM, they must be fixed, sooner rather than later. There's patches in the works which will mean we will end up with IOMMU support in the DMA mapping later, which means everything I've said above will become reality. The patch has been generated using the following coccinelle patch: <smpl> @@ struct scatterlist *sg; @@ -sg_phys(sg) +sg_dma_address(sg) </smpl> Signed-off-by: NLars-Peter Clausen <lars@metafoo.de> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Sachin Kamat 提交于
Removes <linux/interrupt.h> file which was included twice. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Acked-by: NJassi Brar <jaswinder.singh@linaro.org> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Vinod Koul 提交于
the cookie updates completed the cyclic dma descriptor wrongly. This caused the BUG_ON to be hit as submit is called for completed descriptor Fix this by not marking the cyclic descriptor as complete Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com> Tested-by: NThomas Abraham <thomas.abraham@linaro.org>
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由 Huang Shijie 提交于
The current code keeps the callbacks invoked from interrupt context, this does not conform to the Documentation/dmaengine.txt. So add tasklet support to fix this issue. Signed-off-by: NHuang Shijie <b32955@freescale.com> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Viresh Kumar 提交于
SPEAr platforms now support DT and so must convert all drivers to support DT. This patch adds DT probing support for Synopsys DMA controller and updates its documentation too. Signed-off-by: NViresh Kumar <viresh.kumar@st.com> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Viresh Kumar 提交于
clk_{un}prepare is mandatory for platforms using common clock framework. Since this driver is used by SPEAr platform, which supports common clock framework, add clk_{un}prepare() support for it. Signed-off-by: NViresh Kumar <viresh.kumar@st.com> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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- 09 5月, 2012 1 次提交
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由 Andrew Lunn 提交于
Some orion platforms can gate the XOR driver clock. If the clock exisits, unable/disable it as appropriate. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NJamie Lentin <jm@lentin.co.uk> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 25 4月, 2012 5 次提交
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由 Sascha Hauer 提交于
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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由 Sascha Hauer 提交于
the current i.MX clock support groups together unrelated clocks to a single clock which is then used by the driver. This can't be accomplished with the generic clock framework so we instead request the individual clocks in the driver. For i.MX there are generally three different clocks: ipg: bus clock (needed to access registers) ahb: dma relevant clock, sometimes referred to as hclk in the datasheet per: bit clock, pixel clock This patch changes the driver to request the individual clocks. Currently all clk_get will get the same clock until the SoCs are converted to the generic clock framework Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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由 Linus Walleij 提交于
The Nomadik PL080 variant has some extra protection bits that may be set, so we need to check these bits to see if the channels are actually available for the DMAengine to use. Cc: Russell King <linux@arm.linux.org.uk> Cc: Alim Akhtar <alim.akhtar@gmail.com> Cc: Alessandro Rubini <rubini@gnudd.com> Reviewed-by: NViresh Kumar <viresh.kumar@st.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Davide Ciminaghi 提交于
When a client calls pl08x_control with DMA_TERMINATE_ALL, it is correct to terminate and release the phy channel currently in use (if one is in use), but the phychan_hold counter must also be reset (otherwise it could get trapped in an unbalanced state). Signed-off-by: NDavide Ciminaghi <ciminaghi@gnudd.com> Reviewed-by: NViresh Kumar <viresh.kumar@st.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Olof Johansson 提交于
Move a couple of tests and do a minor refactor to avoid: drivers/dma/pl330.c: In function 'pl330_probe': drivers/dma/pl330.c:2929:215: warning: comparison of distinct pointer types lacks a cast [enabled by default] drivers/dma/pl330.c: In function 'pl330_tasklet': drivers/dma/pl330.c:2250:8: warning: 'pch' may be used uninitialized in this function [-Wuninitialized] drivers/dma/pl330.c:2228:25: note: 'pch' was declared here drivers/dma/pl330.c:2277:130: warning: 'pch' may be used uninitialized in this function [-Wuninitialized] drivers/dma/pl330.c:2260:25: note: 'pch' was declared here Signed-off-by: NOlof Johansson <olof@lixom.net> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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- 23 4月, 2012 4 次提交
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由 Linus Walleij 提交于
For some reason I can't figure out we're reading the PL080_INT_STATUS register instead of PL080_TC_STATUS when checking for the terminal count. The PL080_INT_STATUS is a logical OR between the error and terminal count status register and may not report what we want it to, especially if there is an error and a terminal count at the same time and the former is not lowered in time for the check in the TC register. Make sure we read what we're actually interested in. Cc: Russell King <linux@arm.linux.org.uk> Cc: Viresh Kumar <viresh.kumar@st.com> Cc: Alim Akhtar <alim.akhtar@gmail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NViresh Kumar <viresh.kumar@st.com> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Linus Walleij 提交于
A small fallout from Vinod's conversions to dma_transfer_direction, this small comparison was done with a dma_data_direction instead. Fix it by comparing against the correct enum. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Linus Walleij 提交于
The patch "ARM: amba: Remove AMBA level regulator support" breaks the DMA40 driver since the <linux/amba/bus.h> header implicitly included the regulator consumer header. So include it explicitly and fix the build error. Cc: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Narayanan G 提交于
can be directly stopped by issuing a SUSPEND_REQ on the EE bits. There is no need to suspend the physical channel and restart it. Also, the support for pre-V2 hw is discontinued. EE bits for writing: 00: disable only if AS=11 or AS=00 01: enable 10: suspend_req only if AS=01 & EE=01 or EE=11 11: round / no change for writing Signed-off-by: NNarayanan G <narayanan.gopalakrishnan@stericsson.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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- 20 4月, 2012 2 次提交
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由 Nicolas Ferre 提交于
This loop on EBCISR register was designed to clear IRQ sources before enabling a DMA channel. This register is clear-on-read so a race condition can appear if another channel is already active and has just finished its transfer. Removing this read on EBCISR is fixing the issue as there is no case where an IRQ could be pending: we already make sure that this register is drained at probe() time and during resume. Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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由 Shawn Guo 提交于
Enable channel in device_issue_pending call, so that the order between cookie assignment and channel enabling can be ensured naturally. It fixes the mxs gpmi-nand breakage which is caused by the incorrect order of cookie assigning and channel enabling. Suggested-by: NRussell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Tested-by: NHuang Shijie <b32955@freescale.com> Tested-by <samgandhi9@gmail.com> Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
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