timer7 supplies the architected timer and thus as has to run when
the system clocksource and clockevents drivers are registered.

While it should be the responsibility of the bootloader to do this,
and there exists a fix in a community u-boot, all u-boot based systems
that actually shipped have the mentioned issue.

Therefore to not require every developer to update their u-boot, add a
snippet for this, enabling the timer early in the kernel.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The Rockchip support is not limited to Cortex-A9 socs anymore and its
presence may confuse people reading /proc/cpuinfo. So remove the core
specific part.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>

rk3288 SoCs have a function to automatically switch between jtag/sdmmc pinmux
settings depending on the card state. This collides with a lot of assumptions.

It only works when using the internal card-detect mechanism and breaks
horribly when using either the normal card-detect via the slot-gpio function
or via any other pin. Also there is of course no link between the mmc and jtag
on the software-side, so the jtag clocks may very well be disabled when the
card is ejected and the soc switches back to the jtag pinmux.

Leaving the switching function enabled did result in mmc timeouts and rcu
stalls thus hanging the system on 3.19-rc1. Therefore disable it in all cases,
as we expect the devicetree to explicitly select either mmc or jtag pinmuxes
anyway.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>

It's a basic version of suspend and resume for rockchip,
it only support RK3288 now.
Signed-off-by: NTony Xie <xxx@rock-chips.com>
Signed-off-by: NChris Zhong <zyw@rock-chips.com>
Tested-by: NDoug Anderson <dianders@chromium.org>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

cpufreq-cpu0 got renamed to a more generic name cpufreq-dt, so
adapt the created platform-device to this.
Reported-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Rockchip SoCs can sucessfully use the generic cpufreq-cpu0 driver to
do frequency scaling. Therefore add a platform device in the machine
init code.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Enable HAVE_ARM_ARCH_TIMER and add a rockchip,rk3288 compatible.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NWill Deacon <will.deacon@arm.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.  This also allows us to eliminate the
.init_machine function as this becomes the same as the generic version.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

With the newly introduced CPU_METHOD_OF_DECLARE is not necessary anymore
to reference the relevant smp_ops in the board file, but instead it can
simply be set by the enable-method property of the cpu nodes.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>

They're u32, they're not unsigned long.  The UL suffix is not required
here.
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This adds the necessary smp-operations and startup code to use
additional cores on Rockchip SoCs.

We currently hog the power management unit in the smp code, as it is
necessary to control the power to the cpu core and nothing else is
currently using it, so a generic implementation can be done later.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NUlrich Prinz <ulrich.prinz@googlemail.com>

With arch/arm calling of_clk_init(NULL) from time_init(), we can now
remove custom .init_time hooks.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NHeiko Stuebner <heiko@sntech.de>

This adds a generic devicetree board file and a dtsi for boards
based on the RK3066a SoCs from Rockchip.

Apart from the generic parts (gic, clocks, pinctrl) the only components
currently supported are the timers, uarts and mmc ports (all DesignWare-
based).
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NOlof Johansson <olof@lixom.net>