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  1. 19 6月, 2009 1 次提交
  3. 10 6月, 2009 3 次提交
  5. 29 5月, 2009 1 次提交
  7. 03 4月, 2009 5 次提交
  9. 07 1月, 2009 1 次提交
  11. 23 12月, 2008 1 次提交
    • B
      powerpc/cell: add QPACE as a separate Cell platform · def434c2
      由 Benjamin Krill 提交于 
      Since the QPACE (Chromodynamics Parallel Computing on the
Cell Broadband Engine) platform doesn't use a iommu, doesn't
have PCI devices and a MPIC much lesser setup and
configurations are needed. So far all devices are detected
as OF device. A notifier function is used to set the dma_ops
for the of_platform bus. Further this patch splits the
PPC_CELL_NATIVE into PPC_CELL_COMMON which are parts that are
shared with the QPACE platform and the rest.
Signed-off-by: NBenjamin Krill <ben@codiert.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      def434c2
  13. 31 10月, 2008 1 次提交
  15. 26 7月, 2008 1 次提交
    • A
      edac: i5100 new intel chipset driver · 8f421c59
      由 Arthur Jones 提交于 
      Preliminary support for the Intel 5100 MCH.  CE and UE errors are reported
along with the current DIMM label information and other memory parameters.

Reasons why this is preliminary:

1) This chip has 2 independent memory controllers which, for best
   perforance, use interleaved accesses to the DDR2 memory.  This
   architecture does not map very well to the current edac data structures
   which depend on symmetric channel access to the interleaved data.
   Without core changes, the best I could do for now is to map both memory
   controllers to different csrows (first all ranks of controller 0, then
   all ranks of controller 1).  Someone much more familiar with the edac
   core than I will probably need to come up with a more general data
   structure to handle the interleaving and de-interleaving of the two
   memory controllers.

2) I have not yet tackled the de-interleaving of the rank/controller
   address space into the physical address space of the CPU.  There is
   nothing fundamentally missing, it is just ending up to be a lot of
   code, and I'd rather keep it separate for now, esp since it doesn't
   work yet...

3) The code depends on a particular i5100 chip select to DIMM mainboard
   chip select mapping.  This mapping seems obvious to me in order to
   support dual and single ranked memory, but it is not unique and DIMM
   labels could be wrong on other mainboards.  There is no way to query
   this mapping that I know of.

4) The code requires that the i5100 is in 32GB mode.  Only 4 ranks per
   controller, 2 ranks per DIMM are supported.  I do not have hardware
   (nor do I expect to have hardware anytime soon) for the 48GB (6 ranks
   per controller) mode.

5) The serial presence detect code should be broken out into a "real"
   i2c driver so that decode-dimms.pl can work.
Signed-off-by: NArthur Jones <ajones@riverbed.com>
Signed-off-by: NDoug Thompson <dougthompson@xmission.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      8f421c59
  17. 29 4月, 2008 1 次提交
  19. 08 2月, 2008 4 次提交
  21. 27 7月, 2007 2 次提交
  23. 20 7月, 2007 9 次提交
  25. 17 7月, 2007 1 次提交
  27. 10 5月, 2007 1 次提交
  29. 01 4月, 2006 1 次提交
  31. 27 3月, 2006 1 次提交
  33. 10 3月, 2006 1 次提交
  35. 05 2月, 2006 1 次提交
  37. 04 2月, 2006 1 次提交
  39. 19 1月, 2006 1 次提交