1. 17 5月, 2013 2 次提交
    • M
      i2c: designware: always clear interrupts before enabling them · 2a2d95e9
      Mika Westerberg 提交于
      If the I2C bus is put to a low power state by an ACPI method it might pull
      the SDA line low (as its power is removed). Once the bus is put to full
      power state again, the SDA line is pulled back to high. This transition
      looks like a STOP condition from the controller point-of-view which sets
      STOP detected bit in its status register causing the driver to fail
      subsequent transfers.
      
      Fix this by always clearing all interrupts before we start a transfer.
      Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
      Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      Cc: stable@kernel.org
      2a2d95e9
    • J
      i2c: designware: fix RX FIFO overrun · e6f34cea
      Josef Ahmad 提交于
      i2c_dw_xfer_msg() pushes a number of bytes to transmit/receive
      to/from the bus into the TX FIFO.
      For master-rx transactions, the maximum amount of data that can be
      received is calculated depending solely on TX and RX FIFO load.
      
      This is racy - TX FIFO may contain master-rx data yet to be
      processed, which will eventually land into the RX FIFO. This
      data is not taken into account and the function may request more
      data than the controller is actually capable of storing.
      
      This patch ensures the driver takes into account the outstanding
      master-rx data in TX FIFO to prevent RX FIFO overrun.
      Signed-off-by: NJosef Ahmad <josef.ahmad@linux.intel.com>
      Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
      Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      Cc: stable@kernel.org
      e6f34cea
  2. 24 4月, 2013 2 次提交
  3. 20 4月, 2013 4 次提交
  4. 17 4月, 2013 1 次提交
  5. 16 4月, 2013 11 次提交
  6. 09 4月, 2013 2 次提交
  7. 04 4月, 2013 1 次提交
  8. 02 4月, 2013 7 次提交
  9. 29 3月, 2013 3 次提交
  10. 27 3月, 2013 2 次提交
  11. 24 3月, 2013 5 次提交