Introduce imx6sx-sdb-sai.dts so that it is possible to use the
SAI interface.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Property 'dma-source' is not used anywhere, nor it is documented, so
let's just get rid of it.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

According to sdma_peripheral_type in include/linux/platform_data/dma-imx.h
IMX_DMATYPE_SAI corresponds to index 24, so fix it accordingly.
Suggested-by: NZidan Wang <zidan.wang@nxp.com>
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

pwm2 is provided on the BA16 Q7 module, but is not used on any
of the current configurations. However, future platforms may
utilize this device, so we are simply disabling the node rather
than removing it completely.
Signed-off-by: NJustin Waters <justin.waters@timeys.com>
Signed-off-by: NAkshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Based on i.MX6 SoloX with 1GB of RAM.

https://boundarydevices.com/product/nit6_solox-imx6/Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

It is preferred to use the panel compatible string rather than passing the
LCD timings in the device tree.

So pass the "hannstar,hsd100pxn1" compatible string to describe
the LVDS panel on this board.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

This baseboard can be used with all TX6 SoMs, but only a certain set
of combinations can be ordered by default. Add support for these
combinations in mainline, so that users can easily adopt their own
combination of SoM and baseboard themselves.
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add support for the following i.MX6 based modules from Ka-Ro
electronics GmbH:
TX6S-8034:
Processor    Freescale i.MX 6 Solo, 800MHz
RAM          256MiB DDR3 SDRAM
ROM          128MiB NAND Flash
Power supply Single 3.1V to 5.5V
Size         31mm SO-DIMM
Temp. Range  industrial grade (-40°C/-25°C to 105°C Tj)

TX6S-8035:
Processor    Freescale i.MX 6 Solo, 800MHz
RAM          512MiB DDR3 SDRAM
ROM          4GiB eMMC
Power supply Single 3.1V to 5.5V
Size         31mm SO-DIMM
Temp. Range  industrial grade (-40°C/-25°C to 105°C Tj)

TX6U-8033:
Processor    Freescale i.MX 6 Dual Lite, 800MHz
RAM          1GiB DDR3 SDRAM
ROM          4GiB eMMC
Power supply Single 3.1V to 5.5V
Size         31mm SO-DIMM
Temp. Range  industrial grade (-40°C/-25°C to 105°C Tj)

TX6Q-1036:
Processor    Freescale i.MX 6Quad, 1GHz
RAM          1GB DDR3 SDRAM 64-bit
ROM          8GiB eMMC
Power supply Single 3.1V to 5.5V
Size         31mm SO-DIMM
Temp. Range  Extended Consumer Grade (-20°C to 105°C Tj)
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add missing pinctrl for the RTS/CTS lines to uart1 and set the
fsl,uart-has-rtscts property on all UARTs to enable support for HW
handshake.
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Move the pinctrl setting for the board LED from the hoggrp node
to a separate node referenced by the LED driver, so that the pin is
free to be used for different purpose when the LED driver is disabled.
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

DT maintainers don't like the 'simple-bus' container around the
regulator nodes. So remove it.
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Based on i.MX6 Quad Plus with 4GB of RAM.

https://boundarydevices.com/product/nitrogen6max/Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add mdio node and an appropriate PHY configuration to enable use of
the PHY interrupt for link status changes.
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Remove the function node around the pinctrl nodes that was obsoleted
by commit 5fcdf6a7 ("pinctrl: imx: Allow parsing DT without
function nodes"), we can save this container node.

Also move the iomux node to the bottom of the file to improve
readability of the file.
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

The spidev driver doesn't like to be instantiated via a naked 'spidev'
compatible, though it is very convenient to invoke it this way without
a dedicated SPI device for basic functional testing.
Disable the spi node by default to silence the WARN_ON() from the
spidev driver, but leave the configuration intact otherwise.
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add an empty line between properties and subnode in the clocks node.
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

GPLv2-only devicetrees make reuse difficult for software components
licensed under a different license.

The consensus is that a GPL/X11 dual-license should allow all necessary
uses, so relicense the imx6*-tx6* files to this combination.
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

With SION set the level on such a pin is reported to the UART. So for
example when the CS5 pin is configured for GPIO mode and the level
changes this triggers an RTS interrupt on uart5.

Adding some severity to this issue: The imx uart driver currently
doesn't handle correctly irqs for changes on RI and DCD which are
enabled automatically when the respective UART is driven in DTE mode
(that is, has the fsl,dte-mode property set in the device tree). This
results in a stuck machine because the irq isn't cleared and so stalls
the CPU.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Apart from a few additions this also contains two fixes where the daisy
chain input selection register was missing. Moreover dropped _MUX from
some pins for consistency.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Utilize the new PCIe Tx configuration to properly support the correct
values.
Signed-off-by: NJustin Waters <justin.waters@timesys.com>
Signed-off-by: NAkshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

The TXUL-0010/-0011 modules are Computers On Module manufactured by
  Ka-Ro electronics GmbH with the following characteristics:
  Processor    Freescale i.MX 6UltraLite MCIMX6G2, 528 MHz
  RAM          256MB 16-bit DDR3 SDRAM
  ROM          128MB NAND Flash (TXUL-0010) / 4GB eMMC (TXUL-0011)
  Power supply Single 3.3 to 5V
  Size         26mm SO-DIMM
  Temp. Range  -40°C to 85°C
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

If enabling the hsmci regulator on card detection, the board can reboot
on sd card insertion. Keeping the regulator always enabled fixes this
issue.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Fixes: 8d545f32 ("ARM: at91/dt: sama5d4 xplained: add regulators for v(q)mmc1 supplies")
Cc: stable@vger.kernel.org #4.3 and later
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

If enabling the hsmci regulator on card detection, the board can reboot
on sd card insertion. Keeping the regulator always enabled fixes this
issue.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Fixes: 1b53e341 ("ARM: at91/dt: sama5d3 xplained: add fixed regulator for vmmc0")
Cc: stable@vger.kernel.org #4.3 and later
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

This will be needed for UniPhier PH1-LD11 and PH1-LD20 SoCs.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Just for consistent coding style.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Initial commit for PH1-Pro4 Sanji board support.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Initial commit for PH1-Pro4 Ace board support.

Note:
There are two variants for the amount of DDR memory; 1GB or 2GB.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This is used for on-board inter-connection.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This board has an EEPROM (STMicroelectronics M24C64-WMN6TP) connected
to the I2C channel 0 of the SoC.  Its slave address is 0x54.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add master clock nodes generated by crystal oscillators.

  PH1-sLD3, PH1-LD4: 24.576 MHz
  PH1-Pro4, ProXstream2: 25.000 MHz
  PH1-Pro5: 20.000 MHz
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

During the review process of the UniPhier System Bus driver
(drivers/bus/uniphier.c), the current binding of the System Bus
Controller turned out to be no good.  In order to make the driver
really usable, we have to switch over to the new binding defined by
Documentation/devicetree/bindings/bus/uniphier-system-bus.txt.
The old binding will be still supported for a while to keep the
backward compatibility.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This property is used in common by several boards.  Move it to the
common place (uniphier-support-card.dtsi).  If necessary, each board
can still override the property.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This patch adds the emac device node for rk3036 SoCs.
We need to let mac clock under the DPLL which is able to provide
the accurate 50MHz what mac_ref need, since that will cause some
unstable things if the cpufreq is working.
Signed-off-by: NXing Zheng <zhengxing@rock-chips.com>
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Cc: linux-rockchip@lists.infradead.org
Cc: Xing Zheng <zhengxing@rock-chips.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Allow Openblock AX3 using hardware buffer management with mvneta.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Since mvneta driver supports using hardware buffer management (BM), in
order to use it, board files have to be adjusted accordingly. This commit
enables BM on AXP-DB and AXP-GP in same manner - because number of ports
on those boards is the same as number of possible pools, each port is
supposed to use single pool for all kind of packets.

Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
status for 'bm' and 'bm-bppi' (internal SRAM) nodes.
Signed-off-by: NMarcin Wojtas <mw@semihalf.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Armada XP network controller supports hardware buffer management (BM).
Since it is now enabled in mvneta driver, appropriate nodes can be added
to armada-xp.dtsi - for the actual common BM unit (bm@c0000) and its
internal SRAM (bm-bppi), which is used for indirect access to buffer
pointer ring residing in DRAM.

Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.
Signed-off-by: NMarcin Wojtas <mw@semihalf.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Since mvneta driver supports using hardware buffer management (BM), in
order to use it, board files have to be adjusted accordingly. This commit
enables BM on:
* A385-DB-AP - each port has its own pool for long and common pool for
short packets,
* A388-ClearFog - same as above,
* A388-DB - to each port unique 'short' and 'long' pools are mapped,
* A388-GP - same as above.

Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
status for 'bm' and 'bm-bppi' (internal SRAM) nodes.

[gregory.clement@free-electrons.com: add suppport for the ClearFog board]
Signed-off-by: NMarcin Wojtas <mw@semihalf.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Armada 38x network controller supports hardware buffer management (BM).
Since it is now enabled in mvneta driver, appropriate nodes can be added
to armada-38x.dtsi - for the actual common BM unit (bm@c8000) and its
internal SRAM (bm-bppi), which is used for indirect access to buffer
pointer ring residing in DRAM.

Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.
Signed-off-by: NMarcin Wojtas <mw@semihalf.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

The compatible string "simple-bus" is well defined in ePAPR, while
I see no documentation for the "arm,amba-bus" arnywhere in ePAPR or
Documentation/devicetree/.

DT is also used by other projects than Linux kernel.  It is not a
good idea to rely on such an unofficial binding.

This commit
  - replaces "arm,amba-bus" with "simple-bus"
  - drops "arm,amba-bus" where it is used along with "simple-bus"
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>