- 12 6月, 2013 3 次提交
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由 Peter De Schrijver 提交于
Use the correct parents for sclk according to the TRM. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Peter De Schrijver 提交于
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Peter De Schrijver 提交于
The pllp_out2 should be integer only, the fractional bit should always be 0. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 05 6月, 2013 1 次提交
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由 Mikko Perttunen 提交于
The msenc clock's register was set to the usb3 clock's register. Signed-off-by: NMikko Perttunen <mperttunen@nvidia.com> Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 01 6月, 2013 3 次提交
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由 Prashant Gaikwad 提交于
Use common of_clk_init() function for clocks initialization. Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: NThierry Reding <thierry.reding@gmail.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Alexandre Courbot 提交于
Tegra has a blink timer register that allows to modulate the clk_32k clock before outputting it. Since clk_32k is presented to the kernel as a fixed clock, make sure this register does not tamper with the clock frequency and that clk_32k is outputted as-is, similarly to what is done on t20 and t30. Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Prashant Gaikwad 提交于
Number of parents for clk_out_2 and clk_out_3 was incorrectly set to clk_out1_parents. Even though it did not break anything since the size was same better to fix. Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: NThierry Reding <thierry.reding@gmail.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 05 4月, 2013 3 次提交
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由 Stephen Warren 提交于
A gap exists in the binding's clock ID definitions. Fix the clock driver to be consistent. This allows pclk to be looked up through device tree and prevents: ERROR: could not get clock /pmc:pclk(0) Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Peter De Schrijver 提交于
The UART driver enables the console uart clock, so we don't need to do that anymore in this file. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Peter De Schrijver 提交于
Implement clocks for Tegra114. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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