1. 17 4月, 2008 8 次提交
    • R
      IB/core: Add support for "send with invalidate" work requests · 0f39cf3d
      Roland Dreier 提交于
      Add a new IB_WR_SEND_WITH_INV send opcode that can be used to mark a
      "send with invalidate" work request as defined in the iWARP verbs and
      the InfiniBand base memory management extensions.  Also put "imm_data"
      and a new "invalidate_rkey" member in a new "ex" union in struct
      ib_send_wr. The invalidate_rkey member can be used to pass in an
      R_Key/STag to be invalidated.  Add this new union to struct
      ib_uverbs_send_wr.  Add code to copy the invalidate_rkey field in
      ib_uverbs_post_send().
      
      Fix up low-level drivers to deal with the change to struct ib_send_wr,
      and just remove the imm_data initialization from net/sunrpc/xprtrdma/,
      since that code never does any send with immediate operations.
      
      Also, move the existing IB_DEVICE_SEND_W_INV flag to a new bit, since
      the iWARP drivers currently in the tree set the bit.  The amso1100
      driver at least will silently fail to honor the IB_SEND_INVALIDATE bit
      if passed in as part of userspace send requests (since it does not
      implement kernel bypass work request queueing).  Remove the flag from
      all existing drivers that set it until we know which ones are OK.
      
      The values chosen for the new flag is not consecutive to avoid clashing
      with flags defined in the XRC patches, which are not merged yet but
      which are already in use and are likely to be merged soon.
      
      This resurrects a patch sent long ago by Mikkel Hagen <mhagen@iol.unh.edu>.
      Signed-off-by: NRoland Dreier <rolandd@cisco.com>
      0f39cf3d
    • R
      IB/mlx4: Micro-optimize mlx4_ib_post_send() · f438000f
      Roland Dreier 提交于
      Rather than have build_mlx_header() return a negative value on failure
      and the length of the segments it builds on success, add a pointer
      parameter to return the length and return 0 on success.  This matches
      the calling convention used for build_lso_seg() and generates slightly
      smaller code -- eg, on 64-bit x86:
      
      add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-22 (-22)
      function                                     old     new   delta
      mlx4_ib_post_send                           2023    2001     -22
      Signed-off-by: NRoland Dreier <rolandd@cisco.com>
      f438000f
    • E
      IB/mlx4: Add IPoIB LSO support · b832be1e
      Eli Cohen 提交于
      Add TSO support to the mlx4_ib driver.
      Signed-off-by: NEli Cohen <eli@mellanox.co.il>
      Signed-off-by: NRoland Dreier <rolandd@cisco.com>
      b832be1e
    • E
      IB/core: Add creation flags to struct ib_qp_init_attr · b846f25a
      Eli Cohen 提交于
      Add a create_flags member to struct ib_qp_init_attr that will allow a
      kernel verbs consumer to create a pass special flags when creating a QP.
      Add a flag value for telling low-level drivers that a QP will be used
      for IPoIB UD LSO.  The create_flags member will also be useful for XRC
      and ehca low-latency QP support.
      
      Since no create_flags handling is implemented yet, add code to all
      low-level drivers to return -EINVAL if create_flags is non-zero.
      Signed-off-by: NEli Cohen <eli@mellanox.co.il>
      Signed-off-by: NRoland Dreier <rolandd@cisco.com>
      b846f25a
    • E
      IB/mlx4: Add IPoIB checksum offload support · 8ff095ec
      Eli Cohen 提交于
      ConnectX devices support checksum generation and verification of TCP
      and UDP packets for UD IPoIB messages.  This patch checks if the HCA
      supports this and sets the IB_DEVICE_UD_IP_CSUM capability flag if it
      does.  It implements support for handling the IB_SEND_IP_CSUM send
      flag and setting the csum_ok field in receive work completions.
      Signed-off-by: NEli Cohen <eli@mellanox.co.il>
      Signed-off-by: NAli Ayub <ali@mellanox.co.il>
      Signed-off-by: NRoland Dreier <rolandd@cisco.com>
      8ff095ec
    • R
      mlx4_core: Fix confusion between mlx4_event and mlx4_dev_event enums · 37608eea
      Roland Dreier 提交于
      The struct mlx4_interface.event() method was supposed to get an enum
      mlx4_dev_event, but the driver code was actually passing in the
      hardware enum mlx4_event values.  Fix up the callers of
      mlx4_dispatch_event() so that they pass in the right type of value,
      and fix up the event method in mlx4_ib so that it can handle the enum
      mlx4_dev_event values.
      
      This eliminates the need for the subtype parameter to the event
      method, so remove it.
      
      This also fixes the sparse warning
      
          drivers/net/mlx4/intf.c:127:48: warning: mixing different enum types
          drivers/net/mlx4/intf.c:127:48:     int enum mlx4_event  versus
          drivers/net/mlx4/intf.c:127:48:     int enum mlx4_dev_event
      Signed-off-by: NRoland Dreier <rolandd@cisco.com>
      37608eea
    • R
      IB/mlx4: Endianness annotations · d2ae16d5
      Roland Dreier 提交于
      Trivial fixes to stamp_send_wqe().
      Signed-off-by: NRoland Dreier <rolandd@cisco.com>
      d2ae16d5
    • R
      IB/mlx4: Convert "if(foo)" to "if (foo)" · 5d5e815d
      Roland Dreier 提交于
      Signed-off-by: NRoland Dreier <rolandd@cisco.com>
      5d5e815d
  2. 15 2月, 2008 1 次提交
  3. 09 2月, 2008 1 次提交
    • J
      IB/mlx4: Use multiple WQ blocks to post smaller send WQEs · ea54b10c
      Jack Morgenstein 提交于
      ConnectX HCA supports shrinking WQEs, so that a single work request
      can be made of multiple units of wqe_shift.  This way, WRs can differ
      in size, and do not have to be a power of 2 in size, saving memory and
      speeding up send WR posting.  Unfortunately, if we do this then the
      wqe_index field in CQEs can't be used to look up the WR ID anymore, so
      our implementation does this only if selective signaling is off.
      
      Further, on 32-bit platforms, we can't use vmap() to make the QP
      buffer virtually contigious. Thus we have to use constant-sized WRs to
      make sure a WR is always fully within a single page-sized chunk.
      
      Finally, we use WRs with the NOP opcode to avoid wrapping around the
      queue buffer in the middle of posting a WR, and we set the
      NoErrorCompletion bit to avoid getting completions with error for NOP
      WRs.  However, NEC is only supported starting with firmware 2.2.232,
      so we use constant-sized WRs for older firmware.  And, since MLX QPs
      only support SEND, we use constant-sized WRs in this case.
      
      When stamping during NOP posting, do stamping following setting of the
      NOP WQE valid bit.
      Signed-off-by: NMichael S. Tsirkin <mst@dev.mellanox.co.il>
      Signed-off-by: NJack Morgenstein <jackm@dev.mellanox.co.il>
      Signed-off-by: NRoland Dreier <rolandd@cisco.com>
      ea54b10c
  4. 07 2月, 2008 1 次提交
  5. 05 2月, 2008 2 次提交
  6. 26 1月, 2008 1 次提交
    • R
      IB/mlx4: Micro-optimize mlx4_ib_poll_one() · b3226184
      Roland Dreier 提交于
      Rather than byte-swapping cqe->g_mlpath_rqpn each time we extract a
      field from it, byte-swap it once into a temporary variable.  This 
      results in smaller, better code -- eg, on 32-bit x86:
      
      add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-5 (-5)
      function                                     old     new   delta
      mlx4_ib_poll_cq                             1188    1183      -5
      Signed-off-by: NRoland Dreier <rolandd@cisco.com>
      b3226184
  7. 09 1月, 2008 1 次提交
  8. 31 10月, 2007 1 次提交
  9. 19 10月, 2007 1 次提交
  10. 10 10月, 2007 5 次提交
  11. 24 9月, 2007 1 次提交
    • J
      IB/mlx4: Fix data corruption triggered by wrong headroom marking order · 6e694ea3
      Jack Morgenstein 提交于
      This is an addendum to commit 0e6e7416 ("IB/mlx4: Handle new FW
      requirement for send request prefetching").  We also need to handle
      prefetch marking properly for S/G segments, or else the HCA may end up
      processing S/G segments that are not fully written and end up sending
      the wrong data.  This can actually cause data corruption in practice,
      especially on systems with relatively slow CPUs (where the HCA is more
      likely to prefetch while the CPU is in the middle of writing a work
      request into memory).
      
      We write S/G segments in reverse order into the WQE, in order to
      guarantee that the first dword of all cachelines containing S/G
      segments is written last (overwriting the headroom invalidation
      pattern).  The entire cacheline will thus contain valid data when the
      invalidation pattern is overwritten.
      Signed-off-by: NJack Morgenstein <jackm@dev.mellanox.co.il>
      Signed-off-by: NRoland Dreier <rolandd@cisco.com>
      6e694ea3
  12. 16 8月, 2007 1 次提交
  13. 04 8月, 2007 1 次提交
  14. 29 7月, 2007 1 次提交
  15. 21 7月, 2007 2 次提交
  16. 19 7月, 2007 2 次提交
  17. 18 7月, 2007 4 次提交
  18. 13 7月, 2007 2 次提交
  19. 10 7月, 2007 3 次提交
  20. 22 6月, 2007 1 次提交