Convert mmp to use the new sched_clock() infrastructure for extending
32bit counters to full 64-bit nanoseconds.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Convert ixp4xx to use the new sched_clock() infrastructure for
extending 32bit counters to full 64-bit nanoseconds.
Tested-by: NMikael Pettersson <mikpe@it.uu.se>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Provide common sched_clock() infrastructure for platforms to use to
create a 64-bit ns based sched_clock() implementation from a counter
running at a non-variable clock rate.

This implementation is based upon maintaining an epoch for the counter
and an epoch for the nanosecond time.  When we desire a sched_clock()
time, we calculate the number of counter ticks since the last epoch
update, convert this to nanoseconds and add to the epoch nanoseconds.

We regularly refresh these epochs within the counter wrap interval.
We perform a similar calculation as above, and store the new epochs.

We read and write the epochs in such a way that sched_clock() can easily
(and locklessly) detect when an update is in progress, and repeat the
loading of these constants when they're known not to be stable.  The
one caveat is that sched_clock() is not called in the middle of an
update.  We achieve that by disabling IRQs.

Finally, if the clock rate is known at compile time, the counter to ns
conversion factors can be specified, allowing sched_clock() to be tightly
optimized.  We ensure that these factors are correct by providing an
initialization function which performs a run-time check.
Acked-by: NPeter Zijlstra <peterz@infradead.org>
Tested-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: NWill Deacon <will.deacon@arm.com>
Tested-by: NMikael Pettersson <mikpe@it.uu.se>
Tested-by: NEric Miao <eric.y.miao@gmail.com>
Tested-by: NOlof Johansson <olof@lixom.net>
Tested-by: NJamie Iles <jamie@jamieiles.com>
Reviewed-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

MSM doesn't support hotplug, so we prevent it from being
selected in Kconfig.
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

This just adds ARCH_MSM_SCORPIONMP to allow SMP selection for
MSM. MSM is unique in that it doesn't enable SCU or TWD.
Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>

Add the options to enable the function graph tracer on ARM.  Function
graph tracer support requires frame pointers, so exclude Thumb-2 and
also make sure FRAME_POINTER gets enabled when FUNCTION_GRAPH_TRACER is
used, since FUNCTION_TRACER doesn't "select FRAME_POINTER" when
ARM_UNWIND is used.  Therefore, with GCC 4.4.0+, you get plain function
tracing without frame pointers, but you'll need them if you want
function graph tracing.
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRabin Vincent <rabin@rab.in>

This patch fixes followng build warnings.
warning: (ARCH_S5P64X0 && <choice> || ARCH_S5PC100 && <choice> ||
          ARCH_S5PV210 && <choice> || ARCH_S5PV310 && <choice>)
         selects HAVE_S3C_RTC which has unmet direct dependencies (RTC_CLASS)
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch fixes following warnings.
warning: (ARCH_S3C2410 && <choice> || ARCH_S3C64XX && <choice> ||
          ARCH_S5P64X0 && <choice> || ARCH_S5PC100 && <choice> ||
          ARCH_S5PV210 && <choice> || ARCH_S5PV310 && <choice>)
         selects HAVE_S3C2410_I2C which has unmet direct dependencies (I2C)
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Fix build warnings
warning: (ARCH_S3C64XX && <choice> && WATCHDOG || ARCH_S5P64X0 && <choice> && WATCHDOG ||
          ARCH_S5P6442 && <choice> && WATCHDOG || ARCH_S5PC100 && <choice> ||
          ARCH_S5PV210 && <choice> || ARCH_S5PV310 && <choice> || MACH_SMDK6410 && ARCH_S3C64XX)
         selects HAVE_S3C2410_WATCHDOG which has unmet direct dependencies (WATCHDOG)
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: Added fix same warning(mach-s3c64xx/Kconfig)]
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The old apcs-gnu ABI doesn't guarantee that double words are allocated
to registers with even alignment, causing the 64-bit exclusive memory
operations to be rejected by the assembler.

This patch requires that CONFIG_AEABI is set in order to use the native
atomic operations and falls back to the generic (spinlock) code otherwise.
Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch adds ARCH_HAS_CPUFREQ in arch/arm/Kconfig for S5PV210,
and updates mach-s5pv210/Makefile for supporting build CPUFREQ driver.
Signed-off-by: NJaecheol Lee <jc.lee@samsung.com>
Signed-off-by: NSangbeom Kim <sbkim73@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

S5PV310 and S5PC210 support more I2C devices than previous SoCs.
Add the device support code for them.
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Currently, only two operating points: 160Mhz and 800Mhz.
the operating points are tested on babbage 3.0
Signed-off-by: NYong Shen <yong.shen@linaro.org>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Implement cpufreq support for the Tegra SOC.  DVFS is handled by the
core virtual cpu clock.  The frequencies of the two cores are tied
together, the highest frequency requested by either core determines
the actual frequency.
Signed-off-by: NColin Cross <ccross@android.com>

In case of S5PV310/S5PC210, it uses the SPARSEMEM as default memory
configuration. So moved to ARCH_S5PV310 config.
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: edited title]
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

In case of S5PV210/S5PC110, it uses the SPARSEMEM as default memory
configuration. So moved to ARCH_S5PV210 config.
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: edited title]
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds support Watchdog Timer for S5PV310 and S5PC210.
Signed-off-by: NJemings Ko <jemings@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds support RTC for S5PV310 and S5PC210.
Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NJemings Ko <jemings@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Provide a mechanism that allows running code in IRQ context. It is
most useful for NMI code that needs to interact with the rest of the
system -- like wakeup a task to drain buffers.

Perf currently has such a mechanism, so extract that and provide it as
a generic feature, independent of perf so that others may also
benefit.

The IRQ context callback is generated through self-IPIs where
possible, or on architectures like powerpc the decrementer (the
built-in timer facility) is set to generate an interrupt immediately.

Architectures that don't have anything like this get to do with a
callback from the timer tick. These architectures can call
irq_work_run() at the tail of any IRQ handlers that might enqueue such
work (like the perf IRQ handler) to avoid undue latencies in
processing the work.
Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: NKyle McMartin <kyle@mcmartin.ca>
Acked-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
[ various fixes ]
Signed-off-by: NHuang Ying <ying.huang@intel.com>
LKML-Reference: <1287036094.7768.291.camel@yhuang-dev>
Signed-off-by: NIngo Molnar <mingo@elte.hu>

The patch below updates broken web addresses in the arch directory.
Signed-off-by: NJustin P. Mattock <justinmattock@gmail.com>
Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
Cc: Finn Thain <fthain@telegraphics.com.au>
Cc: Randy Dunlap <rdunlap@xenotime.net>
Reviewed-by: NFinn Thain <fthain@telegraphics.com.au>
Signed-off-by: NJiri Kosina <jkosina@suse.cz>

This patch updates the Kconfig and Makefile for the S5P6440 and S5P6450
machines. It also updates arch/arm/ Kconfig and Makefile to include for
support ARCH_S5P64X0 with one kernel image.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add sparse IRQ support in ARCH_MMP.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

In order for CPUidle to work on SMP systems, an implementation of
cpu_idle_wait() is needed.

This patch duplicates the x86 implementation of cpu_idle_wait() for
ARM.
Tested-by: NColin Cross <ccross@android.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com>
Acked-by: NAntonio Ospite <ospite@studenti.unina.it>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Do this by adding flush_icache_all to cache_fns for ARMv6 and 7.
As flush_icache_all may neeed to be called from flush_kern_cache_all,
add it as the first entry in the cache_fns.

Note that now we can remove the ARM_ERRATA_411920 dependency
to !SMP so it can be selected on UP ARMv6 processors, such
as omap2.
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NAnand Gadiyar <gadiyar@ti.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

UP systems do not implement all the instructions that SMP systems have,
so in order to boot a SMP kernel on a UP system, we need to rewrite
parts of the kernel.

Do this using an 'alternatives' scheme, where the kernel code and data
is modified prior to initialization to replace the SMP instructions,
thereby rendering the problematical code ineffectual.  We use the linker
to generate a list of 32-bit word locations and their replacement values,
and run through these replacements when we detect a UP system.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

All platforms which currently support SMP also support the ARM SCU
and ARM TWD blocks, so it's pointless to make these config symbols
conditional on the platform symbols which SMP is already conditional
on.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

On the r2p0, r2p1 and r2p2 versions of the Cortex-A9, data corruption
can occur under very rare conditions due to a store buffer optimisation.

This workaround sets a bit in the diagnostic register of the Cortex-A9,
disabling the optimisation and preventing the problem from occurring.
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>

update OMAP Kconfig help texts for all supported SoC models
Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Signed-off-by: NArnaud Lacombe <lacombar@gmail.com>
Reviewed-by: NSam Ravnborg <sam@ravnborg.org>
Reviewed-by: NMichal Marek <mmarek@suse.cz>

5cfc8ee0 (ARM: convert arm to arch_gettimeoffset()) marked all of
at91 AND at91x40 as needing ARCH_USES_GETTIMEOFFSET, and hence no high
res timer support / accurate clock_gettime() - But only at91x40 needs it.

Cc: stable@kernel.org
Signed-off-by: NPeter Korsgaard <peter.korsgaard@barco.com>
Acked-by: NJohn Stultz <johnstul@us.ibm.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch introduces support for the tcc platform by creating an
arch/arm/plat-tcc and arch/arm/mach-tcc8k directories and adding
basic include files plus Kconfig and Makefile.
Signed-off-by: N"Hans J. Koch" <hjk@linutronix.de>
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

On the r2p0, r2p1 and r2p2 versions of the Cortex-A9, data corruption
can occur if a shared cache line is replaced on one CPU as another CPU
is accessing it.

This workaround sets two bits in the diagnostic register of the Cortex-A9,
reducing the linefill issuing capabilities of the processor and
avoiding the erroneous behaviour.
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

On versions of the Cortex-A9 up to and including r2p2, under rare
circumstances, a DMB instruction between 2 write operations may not
ensure the correct visibility ordering of the 2 writes.

This workaround sets a bit in the diagnostic register of the Cortex-A9,
causing the DMB instruction to behave like a DSB, which functions
correctly on the affected cores.
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Partially revert e69edc79, which introduced automatic zreladdr
support.  The change in the way the manual definition is defined
seems to be error and conflict prone.  Go back to the original way
we were handling this for the time being, while keeping the automatic
zreladdr facility.

Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

If we're targetting a v6 or v7 core and have at least software perf events
available, then automatically add support for hardware breakpoints.

Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: S. Karthikeyan <informkarthik@gmail.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Dynamic ftrace for ARM has been disabled since 07c4cc1c ("ftrace:
disable dynamic ftrace for all archs that use daemon").  Now that the
code has been updated, re-enable it.
Signed-off-by: NRabin Vincent <rabin@rab.in>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

fixes the warning:
.config:369:warning: symbol value '' invalid for ZRELADDR

and the prompt for ZRELADDR on make
Signed-off-by: NErik Gilling <konkers@android.com>

This patch adds default zreladdr of ARCH_S5PV310.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>