Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.

The GPMC node will provide an interrupt controller for the
NAND IRQs.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The NAND Ready/Busy# line is connected to GPMC_WAIT0 pin and
can't be used for wait state insertion for NAND I/O read/write.
So disable read/write wait monitoring as per Reference Manual's
suggestion [1].

[1] dm816x TRM: SPRUGX8C: 9.2.4.12.2 NAND Device-Ready Pin
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.

The GPMC node will provide an interrupt controller for the
NAND IRQs.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The NAND Ready/Busy# line is connected to GPMC_WAIT0 pin and
can't be used for wait state insertion for NAND I/O read/write.
So disable read/write wait monitoring as per Reference Manual's
suggestion [1].

[1] AM335x TRM: SPRUH73L: 7.1.3.3.12.2 NAND Device-Ready Pin

Cc: Teresa Remmet <t.remmet@phytec.de>
Cc: Ilya Ledvich <ilya@compulab.co.il>
Cc: Yegor Yefremov <yegorslists@googlemail.com>
Cc: Rostislav Lisovy <lisovy@gmail.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.

The GPMC node will provide an interrupt controller for the
NAND IRQs.

Cc: Teresa Remmet <t.remmet@phytec.de>
Cc: Ilya Ledvich <ilya@compulab.co.il>
Cc: Yegor Yefremov <yegorslists@googlemail.com>
Cc: Rostislav Lisovy <lisovy@gmail.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The NAND Ready/Busy# line is connected to GPMC_WAIT0 pin and
can't be used for wait state insertion for NAND I/O read/write.
So disable read/write wait monitoring as per Reference Manual's
suggestion [1].

[1] AM437x TRM: SPRUHL7D: 9.1.3.3.12.2 NAND Device-Ready Pin
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.

The GPMC node will provide an interrupt controller for the
NAND IRQs.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

wait pin monitoring is not used for nand so it is pointless to
have the gpmc,wait-monitoring-ns property.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.

The GPMC node will provide an interrupt controller for the
NAND IRQs.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add EEPROM at 0x50 that describes the board configuration.
This is useful for userspace programs that may need to check board
revision and other similar information.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The Logic PD SOM-LV has a USB Host Controller connected to 3-port
hub.  This enables the pin muxing for the host controller and
ehci-phy.
Signed-off-by: NAdam Ford <aford173@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This makes DTS structure more readable.
Signed-off-by: NPali Rohár <pali.rohar@gmail.com>
Acked-By: NSebastian Reichel <sre@kernel.org>
Acked-by: NPavel Machek <pavel@ucw.cz>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The Logic PD DM37xx SOM-LV devkit consists of a base board and a SOM.
While the SOM (System on Module) supports Bluetooth and WiFi, LPD did not
obtain an FCC ID, so anyone who uses it will have to go through certification.

I have only tested the Type 28 Display, SMSC9211 Ethernet, SD/MMC and basic
power management, however the overall current seems high.
Signed-off-by: NAdam Ford <aford173@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The backlight pin is shared with Timer 10 PWM.  This patch allows the
pwm_bl driver to enable the pwm run by this timer to dim the backlight.
Signed-off-by: NAdam Ford <aford173@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add linux,can-disable; to all gpios exported from gpio-keys driver, so
userspace can disable them
Signed-off-by: NIvaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The SoCs on am43x-epos-evm are named am438x.
Hence add the compatibility string and remove the am4372 string.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

OMAP5 has 3 thermal zones cpu, core and multimedia.
On the other hand DRA7 has 5 thermal zones cpu, gpu, core, dspeve
and iva. Currently cpu, core and multimedia are being added via device tree
and the other 2 are getting added via kernel. Add the missing thermal
domains in device tree so we can create the zones with the appropriate
trip numbers, type and temperatures.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Acked-by: NEduardo Valentin <edubezval@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This patch changes a dtsi file to contain the thermal data
for IVA domain. This data will enable a thermal shutdown at 125C.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Acked-by: NEduardo Valentin <edubezval@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This patch changes a dtsi file to contain the thermal data
for DSPEVE domain. This data will enable a thermal shutdown at 125C.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Acked-by: NEduardo Valentin <edubezval@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

DWC3's tx-fifo-resize property has been deprecated
because of it being unnecessary to any HW other than
OMAP5 ES1.0.
Signed-off-by: NFelipe Balbi <balbi@kernel.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This adds an idle pinctrl state, which will be used
by the driver to avoid incoming data during clock
rate changes or data flushing.
Signed-off-By: NSebastian Reichel <sre@kernel.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The MCLK is provided by an external clock of 24.576MHz.
Signed-off-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

UART0 device is the device to be used for boot console output.
Signed-off-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Provide RESET GPIO for the USB PHY, the USB Host port mode and
the PHY device for the controller. Also provides pin multiplexer
information for USB host pins.
Signed-off-by: NPau Pajuel <ppajuel@gmail.com>
Signed-off-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

UART3 device is the device to be used for boot console output.
Signed-off-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This patch defines the pin muxing to configure the hsusb0 through
the twl4030 PMIC, because we can't always assume the bootloader will
do it correctly.
Signed-off-by: NAdam Ford <aford173@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The Nokia N950 and Nokia N9 have a modem attached to their
first ssi port. This change adds the modem to the SSI port.
Signed-off-by: NSebastian Reichel <sre@kernel.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The Nokia N950 and Nokia N9 have a modem attached to their
first ssi port. This change adds all necessary information
to initialize the SSI module, but does not yet add the
modem information.
Signed-off-by: NSebastian Reichel <sre@kernel.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The devkit has an AT25 EEPROM on MCSPI1. Enable this with default
parameters.
Signed-off-by: NAdam Ford <aford173@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Setup regulator and fix pin muxing to allow Panel to sleep and
wake from sleep for some low power improvements.
Signed-off-by: NAdam Ford <aford173@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The Wireless version of the SOM uses an AT24 EEPROM to store product ID.
The EEPROM is readonly.
Signed-off-by: NAdam Ford <aford173@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The Logic PD Torpedo standard kits come with a SOM populated to us an
8-bit parallel camera interface.  This patch pin muxes the omap3-isp
pins, sets the MT9P031 clicks, and configures the i2c2 bus to communicate
with the mt9p031 on address 0x48.

I have not done a lot of testing, but when modprobing
mt9p031, then omap3-isp, the board responds with
MT9P031 detected at address 0x48.
Signed-off-by: NAdam Ford <aford173@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add "syscon-phy-power" property and remove the deprecated "ctrl-module"
property from SATA and USB PHY node. Also remove the unused control
module dt nodes.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The USB2 PHY2 has a different register map compared to USB2 PHY1
to power on/off the PHY. In order to handle it, use the new compatible
string "ti,dra7x-usb2-phy2" for the second instance of USB2 PHY.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add "syscon-phy-power" property and "syscon-pcs" property which can
be used to perform the control module initializations and remove
the deprecated "ctrl-module" property from PCIe PHY dt nodes.

Phandle to "sysclk" clock node is also added to the PCIe PHY node
since some of the syscon initializations is based on system clock
frequency.

Since "omap_control_pcie1phy" and "omap_control_pcie2phy" devicetree
nodes are no longer used, remove it.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add new device tree node for the control module register space where
PCIe registers are present.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add NAND support for dm8148-evm.
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add NAND support for j5-eco evm.
Signed-off-by: NTony Lindgren <tony@atomide.com>