The "sleep.S" file has many functions that be shared by different module
currently. Not just for CPU idle driver. Make it build as default now.
Reported-by: NRhyland Klein <rklein@nvidia.com>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
[swarren: add sleep.o to separate line so each line only contains 1 file]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

It would rather to use the API of time_to_jiffies than a constant number
of jiffies for the wait time of CPU power up.

Based on the work by:
Sang-Hun Lee <sanlee@nvidia.com>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The reset handler code is used for either UP or SMP. To make Tegra device
can compile for UP. It needs to be moved to another file that is not SMP
only. This is because the reset handler also be needed by CPU idle
"powered-down" mode. So we also need to put the reset handler init function
in non-SMP only and init them always.

And currently the implementation of the reset handler to know which CPU is
OK to bring up was identital with "cpu_present_mask". But the
"cpu_present_mask" did not initialize yet when the reset handler init
function was moved to init early function. We use the "cpu_possible_mask"
to replace "cpu_present_mask". Then it can work on both UP and SMP case.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
[swarren: dropped the move of v7_invalidate_l1() from one file to another,
to avoid conflicts with Pavel's cleanup of this function, adjust Makefile
so each line only contains 1 file.]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

There are some redundant codes in the CPUINIT section that was caused by
some codes not be organized well in "headsmp.S". Currently all the codes
in "headsmp.S" were put into CPUINIT section. But actually it doesn't
need to be loacted in CPUINIT section. There is no fuction access them
in CPUINIT section and we will relocate them to IRAM.

These codes also caused some unnecessary functions that access these
codes been put into CPUINIT section too. This patch clean it up and put
them into normal text section.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The tegra_cpu_die was be executed by the CPU itslf. So the clock gating
procedure won't be executed after the CPU hardware shutdown code. Moving
the clock gating procedure to tegra_cpu_kill that will be run by another
CPU after the CPU died.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Updating the cache maintenance order before CPU shutdown when doing CPU
hotplug.
The old order:
* clean L1 by flush_cache_all
* exit SMP
* CPU shutdown
Adapt to:
* disable L1 data cache by clear C bit
* clean L1 by v7_flush_dcache_louis
* exit SMP
* CPU shutdown

For CPU hotplug case, it's no need to do "flush_cache_all". And we should
disable L1 data cache before clean L1 data cache. Then leaving the SMP
coherency.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The power up sequence is different on the cold boot CPU and the CPU
that resumed from the hotplug. For the cold boot CPU, it was been power
gated as default. To power up the cold boot CPU, the power should be
un-gated by un toggling the power gate register manually.

For the CPU that resumed from the hotplug, after un-halted the CPU. The
flow controller will un-gate the power of the CPU. No need to manually
control, just wait the power be resumed and continue the power up
sequence after the CPU power is ready.

Based on the work by:
Varun Wadekar <vwadekar@nvidia.com>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

tegra_cpu_init/exit will be called every time one cpu core is online or
offline. And all cpu cores share same clocks, redundant clk_get/put
wast time,  so I move them out.
Signed-off-by: NRichard Zhao <linuxzsc@gmail.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Fix:

warning: (ARCH_TEGRA_2x_SOC) selects ARM_ERRATA_754327 which has unmet direct dependencies (CPU_V7 && SMP)
warning: (ARCH_TEGRA_2x_SOC) selects ARM_ERRATA_742230 which has unmet direct dependencies (CPU_V7 && SMP)

by selecting options only if SMP.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

No need to be public. Checked with:
  $ touch arch/arm/mach-tegra/*[ch] && make C=1
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Move arch/arm/mach-tegra/timer.c to drivers/clocksource/tegra20_timer.c
so that the code is co-located with other clocksource drivers, and to
reduce the size of the mach-tegra directory.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

CONFIG_HOTPLUG is going away as an option.  As a result, the __dev*
markings need to be removed.

This change removes the use of __devinit, __devexit_p, __devinitdata,
and __devexit from these drivers.

Based on patches originally written by Bill Pemberton, but redone by me
in order to handle some of the coding style issues better, by hand.

Cc: Bill Pemberton <wfp5p@virginia.edu>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Now that the only field in struct sys_timer is .init, delete the struct,
and replace the machine descriptor .timer field with the initialization
function itself.

This will enable moving timer drivers into drivers/clocksource without
having to place a public prototype of each struct sys_timer object into
include/linux; the intent is to create a single of_clocksource_init()
function that determines which timer driver to initialize by scanning
the device dtree, much like the proposed irqchip_init() at:
http://www.spinics.net/lists/arm-kernel/msg203686.html

Includes mach-omap2 fixes from Igor Grinberg.
Tested-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Correct spelling typo within various Kconfig.
Signed-off-by: NMasanari Iida <standby24x7@gmail.com>
Signed-off-by: NJiri Kosina <jkosina@suse.cz>

Since the clk framework has already taken necessary locks before calling
into the arch clk ops code, no further locks are needed while setting
the parent of dsib clk. This patch removes a comment that indicated
otherwise, and yet did not take any locks.
Signed-off-by: NSivaram Nair <sivaramn@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

For Tegra30, pll_p clk's parent is wrongly specified as clk_m instead of
pll_ref in the tegra30_clk_init_table and this is resulting in a
boot-time warning. This patch fixes this by correcting the clk init
table.
Signed-off-by: NSivaram Nair <sivaramn@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Move Tegra's debug-macro.S over to the common debug macro directory.

Move Tegra's debug UART selection menu into ARM's Kconfig.debug, so that
all related options are selected in the same place.

Tegra's uncompress.h is left in mach-tegra/include/mach; it will be
removed whenever Tegra is converted to multi-platform.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

In order to move Tegra's debug-macro.S to a common location for single
zImage, it must not rely on any machine-specific header files such as
<mach/iomap.h>. Duplicate the few physical address definitions that
debug-macro.S relies upon directly into the file.

To avoid tegra_io_desc[] requiring shared knowledge of the UART
mapping's virtual address, use a virtual address outside the ranges
in tegra_io_desc[]. Call debug_ll_io_init() to propagate the mapping
beyond the early pages tables.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Prior to this change, Tegra's debug-macro.S relied on uncompress.h having
determined which UART to use, and whether it was safe to use the UART
(i.e. is it not in reset, and is clocked). This determination was
communicated from uncompress.h to debug-macro.S using a few bytes of
Tegra's IRAM (an on-SoC RAM). This had the disadvantage that uncompress.h
was a required part of the kernel boot process; booting a non-compressed
kernel would not allow earlyprintk to operate.

This change duplicates the UART selection and validation logic into
debug-macro.S so that the reliance on uncompress.h is removed.

This also helps out with single-zImage work, since there is currently no
support for using any uncompress.h with single-zImage.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Delete CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH; it's not useful any more:
* No upstream bootloader currently or will ever support this option.
* CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA is a much more direct alternative.

Merge the fixed and automatic UART selection menus into a single choice
for simplicity; now you either pick AUTO_ODMDATA or a single fixed UART,
rather than potentially having an AUTO option override whatever fixed
option was chosen.

Remove TEGRA_DEBUG_UART_NONE; if you don't want a Tegra DEBUG_LL UART,
simply don't turn on DEBUG_LL. NONE used to be the default option, so
pick AUTO_ODMDATA as the new default.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

SPARSE_IRQ is required for single zImage support.

With this enabled, we can delete <mach/irqs.h>. This requires removing
one unnecessary include of that file, and hard-coding the PCIe IRQ into
the PCIe driver. This is a hack that will be dealt with as part of
converting the PCIe driver into a true DT-supporting driver.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Modify Tegra's timer code to parse the IO address from device tree,
hence removing the dependency on <mach/iomap.h>. This will allow the
driver to be moved to drivers/clocksource/.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Modify Tegra's timer code to parse the Tegra timer IRQ from device tree,
and to instantiate the TWD from device tree, rather than relying on hard-
coded values from <mach/irqs.h>.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This prevents checkpatch complaining when this file is moved in a later
patch.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The L2 RAM is in different power domain from the CPU cluster. So the
L2 content can be retained over CPU suspend/resume. To do that, we
need to disable L2 after the MMU is disabled, and enable L2 before
the MMU is enabled. But the L2 controller is in the same power domain
with the CPU cluster. We need to restore it's settings and re-enable
it after the power be resumed.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This is a power gating idle mode. It support power gating vdd_cpu rail
after all cpu cores in "powered-down" status. For Tegra30, the CPU0 can
enter this state only when all secondary CPU is offline. We need to take
care and make sure whole secondary CPUs were offline and checking the
CPU power gate status. After that, the CPU0 can go into "powered-down"
state safely. Then shut off the CPU rail.

Be aware of that, you may see the legacy power state "LP2" in the code
which is exactly the same meaning of "CPU power down".

Base on the work by:
Scott Williams <scwilliams@nvidia.com>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The flow controller can help CPU to go into suspend mode (powered-down
state). When CPU go into powered-down state, it needs some careful
settings before getting into and after leaving. The enter and exit
functions do that by configuring appropriate mode for flow controller.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add suspend, resume and rail_off_ready API into tegra_cpu_car_ops. These
functions were used for CPU powered-down state maintenance. One thing
needs to notice the rail_off_ready API only availalbe for cpu_g cluster
not cpu_lp cluster.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Enable csite (debug and trace controller) clock at init to prevent it
be disabled. And this also the necessary clock for CPU be brought up or
resumed from a power-gating low power state.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This supports power-gated idle on secondary CPUs for Tegra30. The
secondary CPUs can go into powered-down state independently. When
CPU goes into this state, it saves it's contexts and puts itself
to flow controlled WFI state. After that, it will been power gated.

Be aware of that, you may see the legacy power state "LP2" in the
code which is exactly the same meaning of "CPU power down".

Based on the work by:
Scott Williams <scwilliams@nvidia.com>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The CPU suspending on Tegra means CPU power gating. We add a resume
function for taking care the CPUs that resume from power gating status.
This function was been hooked to the reset handler. We take care
everything here before go into kernel.

Be aware of that, you may see the legacy power status "LP2" in the code
which is exactly the same meaning of "CPU power down".

Based on the work by:
Scott Williams <scwilliams@nvidia.com>
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The different Tegra chips may have different CPU idle states and data.
Individual CPU idle driver make it more easy to maintain.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

For the naming consistency under the mach-tegra, we re-name the file of
"sleep-tXX" to "sleep-tegraXX" (e.g., sleep-t30 to sleep-tegra30).
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The Tegra CPU idle LP3 state is doing ARM WFI only. So it's same with
the common ARM_CPUIDLE_WFI_STATE. Using it to replace LP3 now.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Setup the clock parents for the two display controllers and HDMI.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add the OF_DEV_AUXDATA table entries required to associate the proper
names with host1x and its children. In turn, this allows the devices to
find the required clocks.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Extend the pll_d frequency table with a few entries to support common
HDMI and LVDS display modes and setup the clock parents for the two
display controllers and HDMI.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add the OF_DEV_AUXDATA table entries required to associate the proper
names with host1x and its children. In turn, this allows the devices to
find the required clocks.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This patch adds speedo-based process identification support for Tegra30.
Signed-off-by: NDanny Huang <dahuang@nvidia.com>
[swarren s/Tegra3/Tegra30/ in log print,
s/T30/Tegra30/ in commit description]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Detect CPU and core process ID by checking speedo corner tables.
This can provide a more accurate process ID.
Signed-off-by: NDanny Huang <dahuang@nvidia.com>
[swarren s/Tegra2/Tegra20/ in log print]
Signed-off-by: NStephen Warren <swarren@nvidia.com>