1. 15 8月, 2016 1 次提交
  2. 11 8月, 2016 1 次提交
    • V
      drm/i915: Rewrite fb rotation GTT handling · 6687c906
      Ville Syrjälä 提交于
      Redo the fb rotation handling in order to:
      - eliminate the NV12 special casing
      - handle fb->offsets[] properly
      - make the rotation handling easier for the plane code
      
      To achieve these goals we reduce intel_rotation_info to only contain
      (for each plane) the rotated view width,height,stride in tile units,
      and the page offset into the object where the plane starts. Each plane
      is handled exactly the same way, no special casing for NV12 or other
      formats. We then store the computed rotation_info under
      intel_framebuffer so that we don't have to recompute it again.
      
      To handle fb->offsets[] we treat them as a linear offsets and convert
      them to x/y offsets from the start of the relevant GTT mapping (either
      normal or rotated). We store the x/y offsets under intel_framebuffer,
      and for some extra convenience we also store the rotated pitch (ie.
      tile aligned plane height). So for each plane we have the normal
      x/y offsets, rotated x/y offsets, and the rotated pitch. The normal
      pitch is available already in fb->pitches[].
      
      While we're gathering up all that extra information, we can also easily
      compute the storage requirements for the framebuffer, so that we can
      check that the object is big enough to hold it.
      
      When it comes time to deal with the plane source coordinates, we first
      rotate the clipped src coordinates to match the relevant GTT view
      orientation, then add to them the fb x/y offsets. Next we compute
      the aligned surface page offset, and as a result we're left with some
      residual x/y offsets. Finally, if required by the hardware, we convert
      the remaining x/y offsets into a linear offset.
      
      For gen2/3 we simply skip computing the final page offset, and just
      convert the src+fb x/y offsets directly into a linear offset since
      that's what the hardware wants.
      
      After this all platforms, incluing SKL+, compute these things in exactly
      the same way (excluding alignemnt differences).
      
      v2: Use BIT(DRM_ROTATE_270) instead of ROTATE_270 when rotating
          plane src coordinates
          Drop some spurious changes that got left behind during
          development
      v3: Split out more changes to prep patches (Daniel)
          s/intel_fb->plane[].foo.bar/intel_fb->foo[].bar/ for brevity
          Rename intel_surf_gtt_offset to intel_fb_gtt_offset
          Kill the pointless 'plane' parameter from intel_fb_gtt_offset()
      v4: Fix alignment vs. alignment-1 when calling
          _intel_compute_tile_offset() from intel_fill_fb_info()
          Pass the pitch in tiles in
          stad of pixels to intel_adjust_tile_offset() from intel_fill_fb_info()
          Pass the full width/height of the rotated area to
          drm_rect_rotate() for clarity
          Use u32 for more offsets
      v5: Preserve the upper_32_bits()/lower_32_bits() handling for the
          fb ggtt offset (Sivakumar)
      v6: Rebase due to drm_plane_state src/dst rects
      
      Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NSivakumar Thulasimani <sivakumar.thulasimani@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1470821001-25272-2-git-send-email-ville.syrjala@linux.intel.comAcked-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      6687c906
  3. 05 8月, 2016 5 次提交
  4. 04 8月, 2016 8 次提交
  5. 20 7月, 2016 1 次提交
  6. 27 6月, 2016 1 次提交
  7. 13 6月, 2016 1 次提交
  8. 23 5月, 2016 1 次提交
  9. 11 5月, 2016 1 次提交
  10. 10 5月, 2016 1 次提交
    • V
      drm/i915: Re-enable GGTT earlier during resume on pre-gen6 platforms · ac840ae5
      Ville Syrjälä 提交于
      Move the intel_enable_gtt() call to happen before we touch the GTT
      during resume. Right now it's done way too late. Before
      commit ebb7c78d ("agp/intel-gtt: Only register fake agp driver for gen1")
      it was actually done earlier on account of also getting called from
      the resume hook of the fake agp driver. With the fake agp driver
      no longer getting registered we must move the call up.
      
      The symptoms I've seen on my 830 machine include lowmem corruption,
      other kinds of memory corruption, and straight up hung machine during
      or just after resume. Not really sure what causes the memory corruption,
      but so far I've not seen any with this fix.
      
      I think we shouldn't really need to call this during init, but we have
      been doing that so I've decided to keep the call. However moving that
      call earlier could be prudent as well. Doing it right after the
      intel-gtt probe seems appropriate.
      
      Also tested this on 946gz,elk,ilk and all seemed quite happy with
      this change.
      
      v2: Reorder init_hw vs. enable_hw functions (Chris)
      
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: drm-intel-fixes@lists.freedesktop.org
      Fixes: ebb7c78d ("agp/intel-gtt: Only register fake agp driver for gen1")
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1462559755-353-1-git-send-email-ville.syrjala@linux.intel.comReviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      ac840ae5
  11. 05 5月, 2016 1 次提交
  12. 28 4月, 2016 2 次提交
  13. 31 3月, 2016 1 次提交
    • J
      drm/i915: Refer to GGTT {,VM} consistently · 72e96d64
      Joonas Lahtinen 提交于
      Refer to the GGTT VM consistently as "ggtt->base" instead of just "ggtt",
      "vm" or indirectly through other variables like "dev_priv->ggtt.base"
      to avoid confusion with the i915_ggtt object itself and PPGTT VMs.
      
      Refer to the GGTT as "ggtt" instead of indirectly through chaining.
      
      As a bonus gets rid of the long-standing i915_obj_to_ggtt vs.
      i915_gem_obj_to_ggtt conflict, due to removal of i915_obj_to_ggtt!
      
      v2:
      - Added some more after grepping sources with Chris
      
      v3:
      - Refer to GGTT VM through ggtt->base consistently instead of ggtt_vm
        (Chris)
      
      v4:
      - Convert all dev_priv->ggtt->foo accesses to ggtt->foo.
      
      v5:
      - Make patch checker happy
      
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      72e96d64
  14. 30 3月, 2016 1 次提交
  15. 18 3月, 2016 2 次提交
  16. 01 3月, 2016 1 次提交
  17. 26 2月, 2016 2 次提交
  18. 18 2月, 2016 1 次提交
  19. 06 2月, 2016 1 次提交
    • S
      drm/i915/bxt: Check BIOS RC6 setup before enabling RC6 · 274008e8
      Sagar Arun Kamble 提交于
      RC6 setup is shared between BIOS and Driver. BIOS sets up subset of RC6
      setup registers. If those are not setup Driver should not enable RC6.
      For implementing this, driver can check RC_CTRL0 and RC_CTRL1 values
      to know if BIOS has enabled HW/SW RC6.
      This will also enable user to control RC6 using BIOS settings alone.
      RC6 related instability can be avoided by disabling via BIOS settings
      till driver fixes it.
      
      v2: Had placed logic in gen8 function by mistake. Fixed it.
      Ensuring RPM is not enabled in case BIOS disabled RC6.
      
      v3: Need to disable RPM if RC6 is disabled due to BIOS settings. (Daniel)
      Runtime PM enabling happens before gen9_enable_rc6.
      Moved the updation of enable_rc6 parameter in intel_uncore_sanitize.
      
      v4: Added elaborate check for BIOS RC6 setup. Prepared check_pctx for bxt.
          (Imre)
      
      v5: Caching reserved stolen base and size in the driver private data.
          Reorganized RC6 setup check. Moved from gen9_enable_rc6 to
          intel_uncore_sanitize. (Imre)
      
      v6: Rebasing on the patch submitted by Imre that moves gem_init_stolen
          earlier in the load.
      
      v7: Removed PWRCTX_MAXCNT_VCSUNIT1 check as it applies to SKL. (Imre)
      
      v8: Fixed formatting and checkpatch issues. Fixed functional issue where
          RC6 ctx size check was missing. (Imre)
      
      Cc: Imre Deak <imre.deak@intel.com>
      Signed-off-by: NSagar Arun Kamble <sagar.a.kamble@intel.com>
      Signed-off-by: NImre Deak <imre.deak@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1454697809-22113-1-git-send-email-sagar.a.kamble@intel.com
      274008e8
  20. 29 1月, 2016 1 次提交
  21. 18 1月, 2016 1 次提交
    • T
      drm/i915: Do not call API requiring struct_mutex where it is not available · ca82580c
      Tvrtko Ursulin 提交于
      LRC code was calling GEM API like i915_gem_obj_ggtt_offset from
      places where the struct_mutex cannot be grabbed (irq handlers).
      
      To avoid that this patch caches some interesting bits and values
      in the engine and context structures.
      
      Some usages are also removed where they are not needed like a
      few asserts which are either impossible or have been checked
      already during engine initialization.
      
      Side benefit is also that interrupt handlers and command
      submission stop evaluating invariant conditionals, like what
      Gen we are running on, on every interrupt and every command
      submitted.
      
      This patch deals with logical ring context id and descriptors
      while subsequent patches will deal with the remaining issues.
      
      v2:
       * Cache the VMA instead of the address. (Chris Wilson)
       * Incorporate Dave Gordon's good comments and function name.
      
      v3:
       * Extract ctx descriptor template to a function and group
         functions dealing with ctx descriptor & co together near
         top of the file. (Dave Gordon)
      Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: Dave Gordon <david.s.gordon@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1452870629-13830-1-git-send-email-tvrtko.ursulin@linux.intel.com
      ca82580c
  22. 10 12月, 2015 1 次提交
  23. 19 11月, 2015 2 次提交
  24. 06 10月, 2015 1 次提交
    • M
      drm/i915: prevent out of range pt in the PDE macros (take 3) · 24dfd073
      Michel Thierry 提交于
      We tried to fix this in commit fdc454c1 ("drm/i915: Prevent out of
      range pt in gen6_for_each_pde").
      
      But the static analyzer still complains that, just before we break due
      to "iter < I915_PDES", we do "pt = (pd)->page_table[iter]" with an
      iter value that is bigger than I915_PDES. Of course, this isn't really
      a problem since no one uses pt outside the macro. Still, every single
      new usage of the macro will create a new issue for us to mark as a
      false positive.
      
      Also, Paulo re-started the discussion a while ago [1], but didn't end up
      implemented.
      
      In order to "solve" this "problem", this patch takes the ideas from
      Chris and Dave, but that check would change the desired behavior of the
      code, because the object (for example pdp->page_directory[iter]) can be
      null during init/alloc, and C would take this as false, breaking the for
      loop immediately.
      
      This has been already verified with "static analysis tools".
      
      [1]http://lists.freedesktop.org/archives/intel-gfx/2015-June/068548.html
      
      v2: Make it a single statement, while preventing the common subexpression
      elimination (Chris)
      
      Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Dave Gordon <david.s.gordon@intel.com>
      Signed-off-by: NMichel Thierry <michel.thierry@intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      24dfd073
  25. 23 9月, 2015 1 次提交