Missing bindings were found on running checkpatch.pl on bsc9132
device tree. This patch add/update the following

- Add bindings for L2 cache controller
- Add bindings for memory controller
- Update bindings for USB controller
Signed-off-by: NHarninder Rai <harninder.rai@freescale.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>

 Freescale IFC controller has been used for mpc8xxx. It will be used
 for ARM-based SoC as well. This patch moves the driver to driver/memory
 and fix the header file includes.

  Also remove module_platform_driver() and  instead call
  platform_driver_register() from subsys_initcall() to make sure this module
  has been loaded before MTD partition parsing starts.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

device_type is deprecated and the kernel doesn't require it in most
cases. The only exceptions for flat tree users are the "gianfar",
"ucc_geth" and "ibm,emac" bindings, and arguably that requirement could
be relaxed for ucc_geth and ibm,emac (that is a task for separate
patches though).

This patch removes references to device_type="network" from the binding
documentation where possible and removes the properties from ARM and
microblaze dts files. This patch does not modify the powerpc .dts files
since there are a much larger number of them affected and I think the
ucc_geth, ibm,emac and gianfar users should be addressed before clearing
out the references to reduce the chance of breakage.
Signed-off-by: NGrant Likely <grant.likely@linaro.org>
Acked-by: NMichal Simek <monstr@monstr.eu>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>

device_type is a deprecated property, but some MDIO bus nodes still have
it. Except for a couple of old binding (compatible="gianfar" and
compatible="ucc_geth_phy") the kernel doesn't look for
device_type="mdio" at all.

This patch removes all instances of device_type="mdio" from the binding
documentation and the .dts files.
Signed-off-by: NGrant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>

The linux,phandle property is essentially an internal structural element
of the DT data structure. The dtc toolchain takes care of maintaining it
at compile time. It does not need to appear as part of the binding
documentation. This patch removes it so that users don't think they need
to add a phandle property manually.
Signed-off-by: NGrant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>

Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch adds
the device tree nodes for them.
Signed-off-by: NHongbo Zhang <hongbo.zhang@freescale.com>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

This patch updates the discription of each type of DMA controller and its
channels, it is preparation for adding another new DMA controller binding, it
also fixes some defects of indent for text alignment at the same time.
Signed-off-by: NHongbo Zhang <hongbo.zhang@freescale.com>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Add compatible "fsl,mpic-msi-v4.3" for MPIC v4.3. MPIC v4.3 contains
MSIIR and MSIIR1. MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses different IBS and SRS shift. When using
MSIR1, the interrupt number is not consecutive. It is hard to use
'msi-available-ranges' to describe the ranges of the available
interrupt, so MPIC v4.3 does not support this property.
Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com>
[scottwood@freescale.com: minor grammar fixes]
Signed-off-by: NScott Wood <scottwood@freescale.com>

fsl-ssi was located in powerpc/fsl/ssi.txt. This is no powerpc specific
device, so it should be moved to sound/ as it connects to differen audio
codecs.
Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Tested-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMark Brown <broonie@linaro.org>

The Interlaken is a narrow, high speed channelized chip-to-chip interface. To
facilitate interoperability between a data path device and a look-aside
co-processor, the Interlaken Look-Aside protocol is defined for short
transaction-related transfers. Although based on the Interlaken protocol,
Interlaken Look-Aside is not directly compatible with Interlaken and can be
considered a different operation mode.

The Interlaken LA controller connects internal platform to Interlaken serial
interface. It accepts LA command through software portals, which are system
memory mapped 4KB spaces. The LA commands are then translated into the
Interlaken control words and data words, which are sent on TX side to TCAM
through SerDes lanes.
Signed-off-by: NJoe Liccese <joe.liccese@freescale.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>

-also define a binding for fsl,eref-* properties
Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The PAMU caches use the LIODNs to determine which cache lines hold the
entries for the corresponding LIODs.  The LIODNs must therefore be
carefully assigned to avoid cache thrashing -- two active LIODs with
LIODNs that put them in the same cache line.

Currently, LIODNs are statically assigned by U-Boot, but this has
limitations.  LIODNs are assigned even for devices that may be disabled
or unused by the kernel.  Static assignments also do not allow for device
drivers which may know which LIODs can be used simultaneously.  In
other words, we really should assign LIODNs dynamically in Linux.

To do that, we need to describe the PAMU device and cache topologies in
the device trees.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Acked-by: NStuart Yoder <stuart.yoder@freescale.com>
Acked-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Correct spelling typos within Documentation/devicetree
Signed-off-by: NMasanari Iida <standby24x7@gmail.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The RaidEngine is a new Freescale hardware that used for parity
computation offloading in RAID5/6.

This patch adds the device node in device tree and related binding
documentation.
Signed-off-by: NHarninder Rai <harninder.rai@freescale.com>
Signed-off-by: NNaveen Burmi <naveenburmi@freescale.com>
Signed-off-by: NXuelin Shi <b29237@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Freescale's Integrated Flash controller (IFC) may have one or two
interrupts. In case of single interrupt line, it will cover all IFC
interrupts.

Update this information in IFC device tree bindings
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This binding documents how the message register blocks found in some FSL
MPIC implementations shall be represented in a device tree.
Signed-off-by: NMeador Inge <meador_inge@mentor.com>
Signed-off-by: NJia Hongtao <B38951@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The MSIIR register for each MSI bank is aliased to a different
address. The MSI node reg property was updated to contain this
address:

e.g. reg = <0x41600 0x200 0x44140 4>;

The first region contains the address and length of the MSI
register set and the second region contains the address of
the aliased MSIIR register at 0x44140.
Signed-off-by: NDiana CRACIUN <Diana.Craciun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The FreeScale PowerQUICC-III-compatible (mpc85xx/mpc86xx) MPICs do not
correctly report the number of hardware interrupt sources, so software
needs to override the detected value with "256".

To avoid needing to write custom board-specific code to detect that
scenario, allow it to be easily overridden in the device-tree.
Signed-off-by: NKyle Moffett <Kyle.D.Moffett@boeing.com>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

The Freescale MPIC (and perhaps others in the future) is incapable of
routing non-IPI interrupts to more than once CPU at a time.  Currently
all of the Freescale boards msut pass the MPIC_SINGLE_DEST_CPU flag to
mpic_alloc(), but that information should really be present in the
device-tree.

Older board code can't rely on the device-tree having the property set,
but newer platforms won't need it manually specified in the code.

[BenH: Remove unrelated changes, folded in a different patch]
Signed-off-by: NKyle Moffett <Kyle.D.Moffett@boeing.com>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

The MPIC code checks for a "big-endian" property and sets the flag
MPIC_BIG_ENDIAN if one is present, although prior to the "mpic->flags"
fixup that would never have worked anways.

Unfortunately, even now that it works properly, the Freescale mpic
device-node (the "PowerQUICC-III"-compatible one) does not specify it,
so all of the board ports need to manually pass it to mpic_alloc().

Document the flag and add it to the pq3 device tree.  Existing code will
still need to pass the MPIC_BIG_ENDIAN flag because their dtb may not
have this property, but new platforms shouldn't need to do so.
Signed-off-by: NKyle Moffett <Kyle.D.Moffett@boeing.com>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

This document is created for powerpc rapidio and rmu nodes in dts file.
These nodes can support two rapidio ports and message units. In addition,
It explicates the properties and gives examples about rapidio and rmu nodes.
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NJin Qing <b24347@freescale.com>
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Acked-by: NAlexandre Bounine <alexandre.bounine@idt.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add support for the msi-address-64 property of a PCI node.  This property
specifies the PCI address of MSIIR (message signaled interrupt index
register).

In commit 3da34aae ("powerpc/fsl: Support unique MSI addresses per PCIe Root
Complex"), the msi_addr_hi/msi_addr_lo fields of struct fsl_msi were redefined
from an actual address to just an offset, but the fields were not renamed
accordingly.  These fields are replace with a single field, msiir_offset,
to reflect the new meaning.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Adding new device tree binding file for the DCSR node.  Modifying device
tree dtsi files to add DCSR node for P2041, P3041, P4080, & P5020.
Signed-off-by: NStephen George <stephen.george@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Standarize and document the FPGA nodes used on Freescale QorIQ reference
boards.  There are different kinds of FPGAs used on the boards, but
only two are currently standard: "pixis", "ngpixis", and "qixis".  Although
there are minor differences among the boards that have one kind of FPGA, most
of the functionality is the same, so it makes sense to create common
compatibility strings.

We also need to update the P1022DS platform file, because the compatible
string for its PIXIS node has changed.  This means that older kernels are
not compatible with newer device trees.  This is not a real problem, however,
since that particular function doesn't work anyway.  When the DIU is active,
the PIXIS is in "indirect mode", and so cannot be accessed as a memory-mapped
device.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Since technically it's not powerpc arch-specific.  Also rename it sec2
to differentiate it from its incompatible successor, the SEC 4.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Signed-off-by: NDipen Dudhat <Dipen.Dudhat@freescale.com>
Acked-By: NScott Wood <scottwood@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Update the existing example in the general mpic binding to have a
separate TCRx region.  Currently the example doesn't describe TCRx at
all.  The one upstream device tree with an mpic timer node (p1022ds)
uses one large reg region to describe both, even though there are other
unrelated registers in between.  That device tree also contains a bogus
interrupt specifier, and there's no upstream software that uses this yet,
so changing this shouldn't be a problem.

Add a full binding for the MPIC timer node, not just an example of
4-cell interrupts in the MPIC binding.

Add fsl,available-ranges, similar to msi-available-ranges.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Fixes generated by 'codespell' and manually reviewed.
Signed-off-by: NLucas De Marchi <lucas.demarchi@profusion.mobi>

Adds binding documentation for cache sram for the PQ3 and some QorIQ
based platforms.
Signed-off-by: NVivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Define the binding for compatible = "fsl,mpic", including the definition
of 4-cell interrupt specifiers.  The 3rd and 4th cells are needed to
define additional types of interrupt source outside the "normal" external
and internal interrupts in FSL SoCs.  Define error interrupt, IPIs, and
PIC timer sources.
Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Now handles multiple ranges, doesn't make assumptions about interrupt
specifier format, and doesn't claim interrupts that don't correspond to an
available range.

Also has some better error checking.

The device tree binding is updated to clarify some existing assumptions.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The device tree is used by more than just PowerPC.  Make the documentation
directory available to all.

v2: reorganized files while moving to create arch and driver specific
    directories.
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
Acked-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>