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  1. 24 3月, 2009 17 次提交
  3. 23 3月, 2009 1 次提交
  5. 20 3月, 2009 2 次提交
    • B
      powerpc/mm: Unify PTE_RPN_SHIFT and _PAGE_CHG_MASK definitions · a7d2dac8
      由 Benjamin Herrenschmidt 提交于 
      This updates the 32-bit headers to use the same definitions for the RPN
shift inside the PTE as 64-bit, and thus updates _PAGE_CHG_MASK to
become identical.

This does introduce a runtime visible difference, which is that now,
_PAGE_HASHPTE will be part of _PAGE_CHG_MASK and thus preserved. However
this should have no practical effect as it should have been preserved in
the first place and we got away with not having it there due to our
PTE access functions preserving it anyway.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      a7d2dac8
    • B
      powerpc/mm: Split the various pgtable-* headers based on MMU type · c605782b
      由 Benjamin Herrenschmidt 提交于 
      This patch moves the definition of the PTE format for each MMU type
to separate files instead of all in one file. This improves overall
maintainability and will make it easier to add new types.

On 64-bit, additionally, I've separated the headers relative to the
format of the page table tree (3 vs. 4 levels for 64K vs 4K pages)
from the headers specific to the PTE format for hash based processors,
this will make it easier to add support for Book3 "E" 64-bit
implementations.

There are still some type-related ifdef's in the generic headers,
we might remove them in the long run, but this patch shouldn't result
in any code change, -hopefully- just definitions being moved around.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      c605782b
  7. 19 3月, 2009 6 次提交
  9. 18 3月, 2009 8 次提交
  11. 17 3月, 2009 6 次提交
    • K
      powerpc/mm: Respect _PAGE_COHERENT on classic ppc32 SW · a4bd6a93
      由 Kumar Gala 提交于 
      Since we now set _PAGE_COHERENT in the Linux PTE we shouldn't be clearing
it out before we setup the SW TLB.  Today all the SW TLB machines
(603/e300) that we support are non-SMP, however there are some errata on
some devices that cause us to set _PAGE_COHERENT via CPU_FTR_NEED_COHERENT.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      a4bd6a93
    • P
      powerpc/5200: Enable CPU_FTR_NEED_COHERENT for MPC52xx · c9310920
      由 Piotr Ziecik 提交于 
      BestComm, a DMA engine in MPC52xx SoC, requires snooping when
CPU caches are enabled to work properly.

Adding CPU_FTR_NEED_COHERENT fixes NFS problems on MPC52xx machines
introduced by 'powerpc/mm: Fix handling of _PAGE_COHERENT in BAT setup
code' (sha1: 4c456a67).
Signed-off-by: NPiotr Ziecik <kosmo@semihalf.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      c9310920
    • L
      Fast TSC calibration: calculate proper frequency error bounds · 9e8912e0
      由 Linus Torvalds 提交于 
      In order for ntpd to correctly synchronize the clocks, the frequency of
the system clock must not be off by more than 500 ppm (or, put another
way, 1:2000), or ntpd will end up giving up on trying to synchronize
properly, and ends up reseting the clock in jumps instead.

The fast TSC PIT calibration sometimes failed this test - it was
assuming that the PIT reads always took about one microsecond each (2us
for the two reads to get a 16-bit timer), and that calibrating TSC to
the PIT over 15ms should thus be sufficient to get much closer than
500ppm (max 2us error on both sides giving 4us over 15ms: a 270 ppm
error value).

However, that assumption does not always hold: apparently some hardware
is either very much slower at reading the PIT registers, or there was
other noise causing at least one machine to get 700+ ppm errors.

So instead of using a fixed 15ms timing loop, this changes the fast PIT
calibration to read the TSC delta over the individual PIT timer reads,
and use the result to calculate the error bars on the PIT read timing
properly.  We then successfully calibrate the TSC only if the maximum
error bars fall below 500ppm.

In the process, we also relax the timing to allow up to 25ms for the
calibration, although it can happen much faster depending on hardware.
Reported-and-tested-by: NJesper Krogh <jesper@krogh.cc>
Cc: john stultz <johnstul@us.ibm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: NIngo Molnar <mingo@elte.hu>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      9e8912e0
    • L
      Fix potential fast PIT TSC calibration startup glitch · a6a80e1d
      由 Linus Torvalds 提交于 
      During bootup, when we reprogram the PIT (programmable interval timer)
to start counting down from 0xffff in order to use it for the fast TSC
calibration, we should also make sure to delay a bit afterwards to allow
the PIT hardware to actually start counting with the new value.

That will happens at the next CLK pulse (1.193182 MHz), so the easiest
way to do that is to just wait at least one microsecond after
programming the new PIT counter value.  We do that by just reading the
counter value back once - which will take about 2us on PC hardware.
Reported-and-tested-by: Njohn stultz <johnstul@us.ibm.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      a6a80e1d
    • G
      m68k: merge the non-MMU and MMU versions of siginfo.h · 7a2cf4af
      由 Greg Ungerer 提交于 
      It is trivial to merge the non-MMU and MMU versions of siginfo.h.
Without a single file "make headers_install" is broken for m68k
(since each of the sub-varients of siginfo.h are not installed).
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
      7a2cf4af
    • G
      m68k: use the MMU version of unistd.h for all m68k platforms · 9df3d51b
      由 Greg Ungerer 提交于 
      The MMU version of unistd.h can be use on non-MMU platrorms as well.
Without a single file "make headers_install" is broken for m68k
(since each of the sub-varients of unistd.h are not installed).
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
      9df3d51b