1. 20 9月, 2011 17 次提交
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      drm/nva3/clk: better pll calculation when no fractional fb div available · 52eba8dd
      Ben Skeggs 提交于
      The core/mem/shader clocks don't support the fractional feedback divider,
      causing our calculated clocks to be off by quite a lot in some cases.  To
      solve this we will switch to a search-based algorithm when fN is NULL.
      
      For my NVA8 at PL3, this actually generates identical cooefficients to
      the binary driver.  Hopefully that's a good sign, and that does not
      break VPLL calculation for someone..
      Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
      52eba8dd