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  1. 25 1月, 2008 1 次提交
  3. 24 1月, 2008 6 次提交
    • K
      [POWERPC] Move RapidIO support code from arch/ppc · de3c8d41
      由 Kumar Gala 提交于 
      Do just enough to move the RapidIO support code for 85xx over from arch/ppc
into arch/powerpc and make it still build.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      de3c8d41
    • D
      [POWERPC] 85xx: Respect KERNELBASE, PAGE_OFFSET, and PHYSICAL_START on e500 · e8b63761
      由 Dale Farnsworth 提交于 
      The e500 MMU init code previously assumed KERNELBASE always equaled
PAGE_OFFSET and PHYSICAL_START was 0.  This is useful for kdump
support as well as asymetric multicore.

For the initial kdump support the secondary kernel will run at 32M
but need access to all of memory so we bump the initial TLB up to
64M.  This also matches with the forth coming ePAPR spec.
Signed-off-by: NDale Farnsworth <dale@farnsworth.org>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      e8b63761
    • K
      [POWERPC] Remove update_bridge_resource · 82f0183e
      由 Kumar Gala 提交于 
      The 85xx/86xx pci code no longer uses update_bridge_resource and it was the
only caller.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      82f0183e
    • K
      [POWERPC] Fixup transparent P2P resources · b188b2ae
      由 Kumar Gala 提交于 
      For transparent P2P bridges the first 3 resources may get set from based on
BAR registers and need to get fixed up. Where as the remainder come from the
parent bus and have already been fixed up.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      b188b2ae
    • K
      [POWERPC] Ensure we only handle PowerMac PCI bus fixup for memory resources · 96d69c31
      由 Kumar Gala 提交于 
      The fixup code that handles the case for PowerMac's that leave bridge
windows open over an inaccessible region should only be applied to
memory resources (IORESOURCE_MEM).  If not we can get it trying to fixup
IORESOURCE_IO on some systems since the other conditions that are used to
detect the case can easily match for IORESOURCE_IO.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      96d69c31
    • P
      [POWERPC] Provide a way to protect 4k subpages when using 64k pages · fa28237c
      由 Paul Mackerras 提交于 
      Using 64k pages on 64-bit PowerPC systems makes life difficult for
emulators that are trying to emulate an ISA, such as x86, which use a
smaller page size, since the emulator can no longer use the MMU and
the normal system calls for controlling page protections.  Of course,
the emulator can emulate the MMU by checking and possibly remapping
the address for each memory access in software, but that is pretty
slow.

This provides a facility for such programs to control the access
permissions on individual 4k sub-pages of 64k pages.  The idea is
that the emulator supplies an array of protection masks to apply to a
specified range of virtual addresses.  These masks are applied at the
level where hardware PTEs are inserted into the hardware page table
based on the Linux PTEs, so the Linux PTEs are not affected.  Note
that this new mechanism does not allow any access that would otherwise
be prohibited; it can only prohibit accesses that would otherwise be
allowed.  This new facility is only available on 64-bit PowerPC and
only when the kernel is configured for 64k pages.

The masks are supplied using a new subpage_prot system call, which
takes a starting virtual address and length, and a pointer to an array
of protection masks in memory.  The array has a 32-bit word per 64k
page to be protected; each 32-bit word consists of 16 2-bit fields,
for which 0 allows any access (that is otherwise allowed), 1 prevents
write accesses, and 2 or 3 prevent any access.

Implicit in this is that the regions of the address space that are
protected are switched to use 4k hardware pages rather than 64k
hardware pages (on machines with hardware 64k page support).  In fact
the whole process is switched to use 4k hardware pages when the
subpage_prot system call is used, but this could be improved in future
to switch only the affected segments.

The subpage protection bits are stored in a 3 level tree akin to the
page table tree.  The top level of this tree is stored in a structure
that is appended to the top level of the page table tree, i.e., the
pgd array.  Since it will often only be 32-bit addresses (below 4GB)
that are protected, the pointers to the first four bottom level pages
are also stored in this structure (each bottom level page contains the
protection bits for 1GB of address space), so the protection bits for
addresses below 4GB can be accessed with one fewer loads than those
for higher addresses.
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      fa28237c
  5. 17 1月, 2008 7 次提交
  7. 15 1月, 2008 1 次提交
    • B
      [POWERPC] Workaround for iommu page alignment · d262c32a
      由 Benjamin Herrenschmidt 提交于 
      Commit 5d2efba6 changed our iommu code
so that it always uses an iommu page size of 4kB.  That means with our
current code, drivers may do a dma_map_sg() of a 64kB page and obtain
a dma_addr_t that is only 4k aligned.

This works fine in most cases except for some infiniband HW it seems,
where they tell the HW about the page size and it ignores the low bits
of the DMA address.

This works around it by making our IOMMU code enforce a PAGE_SIZE alignment
for mappings of objects that are page aligned in the first place and whose
size is larger or equal to a page.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      d262c32a
  9. 10 1月, 2008 1 次提交
  11. 31 12月, 2007 1 次提交
  13. 24 12月, 2007 6 次提交
  15. 21 12月, 2007 5 次提交
  17. 20 12月, 2007 12 次提交