1. 07 7月, 2016 1 次提交
  2. 04 7月, 2016 1 次提交
  3. 30 6月, 2016 1 次提交
  4. 13 6月, 2016 5 次提交
  5. 30 5月, 2016 1 次提交
  6. 23 5月, 2016 2 次提交
  7. 13 5月, 2016 1 次提交
  8. 09 5月, 2016 1 次提交
  9. 04 5月, 2016 2 次提交
  10. 29 4月, 2016 1 次提交
  11. 27 4月, 2016 2 次提交
  12. 22 4月, 2016 3 次提交
  13. 21 4月, 2016 1 次提交
  14. 19 4月, 2016 1 次提交
    • I
      drm/i915/ddi: Fix eDP VDD handling during booting and suspend/resume · bf93ba67
      Imre Deak 提交于
      The driver's VDD on/off logic assumes that whenever the VDD is on we
      also hold an AUX power domain reference. Since BIOS can leave the VDD on
      during booting and resuming and on DDI platforms we won't take a
      corresponding power reference, the above assumption won't hold on those
      platforms and an eventual delayed VDD off work will do an extraneous AUX
      power domain put resulting in a refcount underflow. Fix this the same
      way we did this for non-DDI DP encoders:
      
      commit 6d93c0c4 ("drm/i915: fix VDD state tracking after system
      resume")
      
      At the same time call the DP encoder suspend handler the same way as the
      non-DDI DP encoders do to flush any pending VDD off work. Leaving the
      work running may cause a HW access where we don't expect this (at a point
      where power domains are suspended already).
      
      While at it remove an unnecessary function call indirection.
      
      This fixed for me AUX refcount underflow problems on BXT during
      suspend/resume.
      
      CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
      CC: stable@vger.kernel.org
      Signed-off-by: NImre Deak <imre.deak@intel.com>
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1460963062-13211-4-git-send-email-imre.deak@intel.com
      bf93ba67
  15. 15 4月, 2016 5 次提交
  16. 04 4月, 2016 1 次提交
  17. 02 4月, 2016 1 次提交
    • V
      drm/i915: Disable FDI RX before DDI_BUF_CTL · 5b421c57
      Ville Syrjälä 提交于
      Bspec is confused w.r.t. the HSW/BDW FDI disable sequence. It lists
      FDI RX disable both as step 13 and step 18 in the sequence. But I dug
      up an old BUN mail from Art that moved the FDI RX disable to happen
      before DDI_BUF_CTL disable. That BUN did not renumber the steps and just
      added a note:
      "Workaround: Disable PCH FDI Receiver before disabling DDI_BUF_CTL."
      
      The BUN described the symptoms of the fixed issue as:
      "PCH display underflow and a black screen on the analog CRT port that
      happened after a FDI re-train"
      
      I suppose later someone tried to renumber the steps to match, but forgot
      to remove the FDI RX disable from its old position in the sequence.
      
      They also forgot to update the note describing what should be done in
      case of an FDI training failure. Currently it says:
      "To retry FDI training, follow the Disable Sequence steps to Disable FDI,
      but skip the steps related to clocks and PLLs (16, 19, and 20), ..."
      
      It should really say "17, 20, and 21" with the current sequence because
      those are the steps that deal with PLLs and whatnot, after step 13 became
      FDI RX disable. And had the step 18 FDI RX disable been removed, as I
      suspect it should have, the note should actually say "17, 19, and 20".
      
      So, let's move the FDI RX disable to happen before DDI_BUF_CTL disable,
      as that would appear to be the correct order based on the BUN.
      
      Note that Art has since unconfused the spec, and so this patch should
      now match the steps listed in the spec.
      
      v2: Add a note that the spec is now correct
      
      Cc: Paulo Zanoni <przanoni@gmail.com>
      Cc: Art Runyan <arthur.j.runyan@intel.com>
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1456841783-4779-1-git-send-email-ville.syrjala@linux.intel.comReviewed-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      5b421c57
  18. 01 4月, 2016 2 次提交
  19. 29 3月, 2016 2 次提交
  20. 21 3月, 2016 1 次提交
  21. 09 3月, 2016 5 次提交