Add node for the Xilinx A/D Converter.

Cc: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The Zynq UART is Cadence IP and the driver has been renamed accordingly.
Migrate the DT to use the new binding for the UART driver.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: NRob Herring <robh@kernel.org>
Tested-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Provide information through SOC_BUS to user space.
Silicon revision is provided through devcfg device.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

To silence the warning
	cpufreq_cpu0: failed to get cpu0 regulator: -19
from the cpufreq driver regarding a missing regulator,
add a fixed regulator to the DT.
Zynq does not support voltage scaling and the CPU rail should always be
supplied with 1 V, hence it is added in the SOC-level dtsi.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

 - Use generic node names
 - Fix up some weird formatting and white spaces
 - Update copyright info
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>

This is likely a copy-and-paste error from the
ARM GIC documentation, that has already been fixed.

address-cells should have been set to 0, as with the size
cells. As having those properties set to 0 is the
same thing as not specifying them, drop them completely.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Tested-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Specify the 'clock-latency' property to avoid certain cpufreq governors
from refusing to work with the following error:
  ondemand governor failed, too long transition latency of HW, fallback to performance governor
Reported-by: NMike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Tested-by: NMike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The generic cpufreq-cpu0 driver can scale the CPU frequency on Zynq
SOCs. Add the required platform device to the BSP and appropriate
OPPs to the dts.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: devicetree@vger.kernel.org
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

The clkc has its registers in the range of the slcr.
Instead of passing around the slcr base address pointer, let the clkc get the
address from the DT.
This prepares the slcr to be a real driver with multiple memory ranges
(slcr, clocks, pinctrl,...)
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Split the slcr into an early part for unlocking and cpu starting
and a later syscon driver.
Also add "syscon" compatible property for slcr.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add nodes for the Arasan SDHCI controller to Zynq dts files.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Add a 'cpus' node to describe the CPU cores of Zynq.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The bindings for the TTC changed in commit 'arm: zynq: Use standard
timer binding' (e932900a). That change
removed possible subnodes from this driver rendering the 'clock-ranges'
property invalid for this node.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The zynq includes a Cadence GEM IP core. This is compatible with the macb driver.
Add it to the zynq-7000 DT.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Josh Cartwright <josh.cartwright@ni.com>
[soren: rebased to current Linus tree, added zc706 + zed support, moved phy-mode property to board level dtses]
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Zynq is based on an ARM Cortex-A9 MPCore, which features the
arm_global_timer in its SCU. Therefore enable the timer for Zynq.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Set the default status for UARTs to disabled in the zynq-7000.dtsi file
and let board dts files enable the UARTs on demand.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Migrate the Zynq platform and its drivers to use the new clock
controller driver.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jslaby@suse.cz>
Cc: linux-serial@vger.kernel.org
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NMike Turquette <mturquette@linaro.org>

The zynq has a Cortex-A9 with the corresponding smp_twd timers. Use them.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Zynq is standard PMU with 2 interrupt per core.
There is also access via register which is not used right now.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Use cdns,ttc because this driver is Cadence Rev06
Triple Timer Counter and everybody can use it
without xilinx specific function name or probing.

Also use standard dt description for timer
and also prepare for moving to clocksource
initialization.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add support for specifying clock information for the uart clk via the
device tree. This eliminates the need to hardcode rates in the device
tree.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Add support for retrieving TTC configuration from device tree.  This
includes the ability to pull information about the driving clocks from
the of_clk bindings.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

Make the Zynq platform use the newly created zynq clk bindings.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

The purpose of the created zynq-7000.dtsi file is to describe the
hardware common to all Zynq 7000-based boards.  Also, get rid of the
zynq-ep107 device tree, since it is not hardware anyone can purchase.

Add a zc702 dts file based on the zynq-7000.dtsi.  Add it to the
dts/Makefile so it is built with the 'dtbs' target.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

The zynq-7000 has an additional UART at 0xE0001000.  Describe it in the
device tree.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

The Zynq has a PL310 L2 cache controller.  Convert in-tree uses to using
the device tree.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Cc: John Linn <john.linn@xilinx.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Tested-by: NMichal Simek <michal.simek@xilinx.com>

The Zynq uses the cortex-a9-gic.  This eliminates the need to hardcode
register addresses.
Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com>
Cc: John Linn <john.linn@xilinx.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Tested-by: NMichal Simek <michal.simek@xilinx.com>

The 1st board support is minimal to get a system up and running
on the Xilinx platform.

This platform reuses the clock implementation from plat-versatile, and
it depends entirely on CONFIG_OF support.  There is only one board
support file which obtains all device information from a device tree
dtb file which is passed to the kernel at boot time.
Signed-off-by: NJohn Linn <john.linn@xilinx.com>