pxa_gpio_irq_type() and pxa_unmask_muxed_gpio() will touch non-muxed GPIOs
(0 and 1 on PXA2xx/PXA3xx) bits in GRERx and GFERx, which is incorrect.
Actually, only those bits should get updated if the corresponding bits are
set in c->irq_mask as well. Fix this by updating only those relevant bits.
Reported-and-tested-by: NDaniel Ribeiro <drwyrm@gmail.com>
Signed-off-by: NEric Miao <eric.miao@marvell.com>

1. add common GPIO handling code into [arch/arm/plat-pxa]

2. common code in <mach/gpio.h> moved into <plat/gpio.h>, new processors
   should implement its own <mach/gpio.h>, provide the following required
   definitions and '#include <plat/gpio.h>' in the end:

   - GPIO_REGS_VIRT for mapped virtual address of the GPIO registers'
     physical I/O memory

   - macros of GPLR(), GPSR(), GPDR() for constant optimization for
     functions gpio_{set,get}_value() (so that bit-bang code can still
     have tolerable performance)

   - NR_BUILTIN_GPIO for the number of onchip GPIO

   - definitions of __gpio_is_inverted() and __gpio_is_occupied(), they
     can be either macros or inlined functions
Signed-off-by: NEric Miao <eric.miao@marvell.com>

Let's handle GPIOs by banks, each bank covers up to 32 GPIOs with one set
of registers, and each set of registers start from different offsets.

           GPLR    GPDR    GPSR    GPCR    GRER    GFER    GEDR
 BANK 0 - 0x0000  0x000C  0x0018  0x0024  0x0030  0x003C  0x0048
 BANK 1 - 0x0004  0x0010  0x001C  0x0028  0x0034  0x0040  0x004C
 BANK 2 - 0x0008  0x0014  0x0020  0x002C  0x0038  0x0044  0x0050

 BANK 3 - 0x0100  0x010C  0x0118  0x0124  0x0130  0x013C  0x0148
 BANK 4 - 0x0104  0x0110  0x011C  0x0128  0x0134  0x0140  0x014C
 BANK 5 - 0x0108  0x0114  0x0120  0x012C  0x0138  0x0144  0x0150

 NOTE:
   BANK 3 is only available on PXA27x and later processors.
   BANK 4 and 5 are only available on PXA935

1. introduce GPIO_BANK(n) for the offset base of each bank

2. 'struct pxa_gpio_chip' is expanded to include IRQ edge and mask
   setings, and saved register values as well, and is dynamically
   allocated due to possible bank number ranging from 3 to 6

3. all accesses to GPIO registers are made through 'regbase' within
   'pxa_gpio_chip', and register offset

4. introduce several inline functions to simplify the code a bit

5. change IRQ demux handler to base on gpio chips
Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Signed-off-by: NEric Miao <eric.miao@marvell.com>

Signed-off-by: NEric Miao <eric.miao@marvell.com>

This makes gpio.c fully independent of pxa-regs.h (except for the
virtual address of the registers).
Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Signed-off-by: NEric Miao <eric.miao@marvell.com>

Looks like we have to live with pxa_gpio_mode() for a while, giving
its presence is actually making gpio.c not generic enough, let's
move it temporarily outside before it can be fully purged.
Signed-off-by: NEric Miao <eric.miao@marvell.com>

This is part of the work making gpio.c generic enough, the changes
include:

1. move IRQ handling of GPIO 0 and 1 outside (and back into irq.c)

2. pxa_init_gpio() accepts a range for muxed GPIO IRQs, and an IRQ
   number for the muxed GPIOs

3. __gpio_is_occupied() and __gpio_is_inverted() are made inline,
   and are moved into <mach/gpio.h> instead of generic gpio.c
Signed-off-by: NEric Miao <eric.miao@marvell.com>

Signed-off-by: NEric Miao <eric.miao@marvell.com>

Original patch from Marek Vasut, the problems with PXA26x are:

1. there are additional 4 GPIOs 86,87,88,89 have their direction bits
   inverted in GPDR2, as well as their alternate function bits being
   '1' for their GPIO functionality in GAFRx

2. there is no easy way to decide if the processor is a pxa26x or a
   pxa250/pxa255 at run-time, so the assumption here is the pxa26x
   will be treated as one of the pxa25x variants, and board code
   should have a better knowledge of the processor it is featured

Introduce pxa26x_init_irq() for the second purpose, and treat the
additional GPIOs > 85 on PXA25x specially.

Kconfig option CONFIG_CPU_PXA26x is introduced to optimize the code
a bit when PXA26x support isn't needed. Board config options have
to select this to enable the support for PXA26x.

__gpio_is_inverted() will be optimized way when CONFIG_CPU_PXA26x
isn't selected.
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NEric Miao <eric.miao@marvell.com>

desc_handle_irq() was declared as obsolete since long ago.
Replace it with generic_handle_irq()
Signed-off-by: NDmitry Baryshkov <dbaryshkov@gmail.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This just leaves include/asm-arm/plat-* to deal with.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Remove includes of asm/hardware.h in addition to asm/arch/hardware.h.
Then, since asm/hardware.h only exists to include asm/arch/hardware.h,
update everything to directly include asm/arch/hardware.h and remove
asm/hardware.h.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Shut up sparse warnings by making GPIO_IRQ_MASK unisgned
Signed-off-by: NDmitry Baryshkov <dbaryshkov@gmail.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

two reasons:
1. GPIO namings and their mode definitions are conceptually not part
   of the PXA register definitions

2. this is actually a temporary move in the transition of PXA2xx to
   use MFP-alike APIs (as what PXA3xx is now doing), so that legacy
   code will still work and new code can be added in step by step
Signed-off-by: Neric miao <eric.miao@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The main issue here is that pxa3xx does not have GAFRx registers,
access directly to these registers should be avoided for pxa3xx:

1. introduce __gpio_is_occupied() to indicate the GAFRx and GPDRx
   registers are already configured on pxa{25x,27x} while returns
   0 always on pxa3xx

2. pxa_gpio_mode(gpio | GPIO_IN) is replaced directly with assign-
   ment of GPDRx, the side effect of this change is that the pin
   _must_ be configured before use, pxa_gpio_irq_type() will not
   change the pin to GPIO, as this restriction is sane, esp. with
   the new MFP framework
Signed-off-by: Neric miao <eric.miao@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: Neric miao <eric.miao@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

To further clean up the GPIO and IRQ structure:

1. pxa_init_irq_gpio() and pxa_init_gpio() combines into a single
   function pxa_init_gpio()

2. assignment of set_wake merged into pxa_init_{irq,gpio}() as
   an argument
Signed-off-by: Neric miao <eric.miao@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: Neric miao <eric.miao@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: Neric miao <eric.miao@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This adds gpiolib support for the PXA architecture:
  - move all GPIO API functions from generic.c into gpio.c
  - convert the gpio_get/set_value macros into inline functions

This makes it easier to hook up GPIOs provided by external chips like
ASICs and CPLDs.
Signed-off-by: NPhilipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Cc: Jean Delvare <khali@linux-fr.org>
Cc: Eric Miao <eric.miao@marvell.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Haavard Skinnemoen <hskinnemoen@atmel.com>
Cc: Ben Gardner <bgardner@wabtec.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
[ Minor ARM fixup from David Brownell folded into this ]
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>