Fixes generated by 'codespell' and manually reviewed.
Signed-off-by: NLucas De Marchi <lucas.demarchi@profusion.mobi>

The original version has many duplicated codes for null/u8/u16 case,
so unify them to make it cleaner
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

include/linux/dw_spi.h only includes driver internal data.  It doesn't
expose a platform_data configuration structure or similar (at least
nothing in-tree).  This patch moves the header into drivers/spi so
that the scope is limited to only the dw_spi_*.c driver files
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
Cc: Feng Tang <feng.tang@intel.com>
Cc: spi-devel-general@lists.sourceforge.net

Currently, build on PPC dies with:
In file included from drivers/spi/dw_spi_mmio.c:16:
include/linux/spi/dw_spi.h:147: error: field ‘tx_sgl’ has incomplete type
include/linux/spi/dw_spi.h:149: error: field ‘rx_sgl’ has incomplete type

Add linux/scatterlist.h include to dw_spi.h, because we need to know
the contents of the structure.
Signed-off-by: NJiri Slaby <jslaby@suse.cz>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

dw_spi driver in upstream only supports PIO mode, and this patch
will support it to cowork with the Designware dma controller used
on Intel Moorestown platform, at the same time it provides a general
framework to support dw_spi core to cowork with dma controllers on
other platforms

It has been tested with a Option GTM501L 3G modem and Infenion 60x60
modem. To use DMA mode, DMA controller 2 of Moorestown has to be enabled

Also change the dma interface suggested by Linus Walleij.
Acked-by: NLinus Walleij <linus.walleij@stericsson.com>
Signed-off-by: NFeng Tang <feng.tang@intel.com>
[Typo fix and renames to match intel_mid_dma renaming]
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
Signed-off-by: NAlan Cox <alan@linux.intel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

commit 052dc7c4i "spi/dw_spi: conditional transfer mode change"
introduced cs_control code, which has a bug by using bit offset
for spi mode to set transfer mode in control register. Also it
forces devices who don't need cs_control to re-configure the
control registers for each spi transfer. This patch will fix them
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The driver core allows for a platform-specific chipselect assert/deassert
function, however the chipselect function in the core doesn't take advantage
of this fact.

This enables the use of a custom function, should it be defined.
Signed-off-by: NGeorge Shore <george@georgeshore.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Now dw_spi core fully supports 3 transfer modes: pure polling,
DMA and IRQ mode. IRQ mode will use the FIFO half empty as
the IRQ trigger, so each interface driver need set the fifo_len,
so that core driver can handle it properly
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Driver for the Designware SPI core, it supports multipul interfaces like
PCI/APB etc.  User can use "dw_apb_ssi_db.pdf" from Synopsys as HW
datasheet.

[randy.dunlap@oracle.com: fix build]
[akpm@linux-foundation.org: build fix]
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: NRandy Dunlap <randy.dunlap@oracle.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>