1. 04 1月, 2014 1 次提交
  2. 31 12月, 2013 1 次提交
  3. 16 12月, 2013 1 次提交
    • P
      ahci: bail out on ICH6 before using AHCI BAR · 6fec8871
      Paul Bolle 提交于
      The check for "combined mode" (which disables ahci support) on ICH6 is
      done after the first use of AHCI BAR. But if ahci is not enabled AHCI
      BAR is initialized to 0x00000000. (At least it is on the ICH6-M I tested
      this on. If I understand the datasheet correctly it should also be on
      ICH6R.) This apparently makes the call of
      pcim_iomap_regions_request_all() return -EINVAL. And we end up with
          ahci: probe of 0000:00:1f.2 failed with error -22
      
      (at warning level) in the logs.
      
      So check for "combined mode" before calling
      pcim_iomap_regions_request_all().
      Signed-off-by: NPaul Bolle <pebolle@tiscali.nl>
      Signed-off-by: NTejun Heo <tj@kernel.org>
      6fec8871
  4. 15 12月, 2013 1 次提交
  5. 23 11月, 2013 2 次提交
  6. 05 11月, 2013 1 次提交
  7. 08 10月, 2013 1 次提交
  8. 25 8月, 2013 1 次提交
  9. 23 7月, 2013 1 次提交
  10. 25 6月, 2013 1 次提交
  11. 22 6月, 2013 1 次提交
  12. 04 6月, 2013 1 次提交
  13. 03 6月, 2013 1 次提交
  14. 29 5月, 2013 1 次提交
  15. 22 5月, 2013 1 次提交
  16. 15 5月, 2013 1 次提交
  17. 16 4月, 2013 1 次提交
  18. 05 3月, 2013 1 次提交
  19. 21 2月, 2013 1 次提交
  20. 26 1月, 2013 1 次提交
  21. 25 1月, 2013 1 次提交
    • A
      AHCI: Support multiple MSIs · 5ca72c4f
      Alexander Gordeev 提交于
      Take advantage of multiple MSIs implementation on x86 - on
      systems with IRQ remapping AHCI ports not only get assigned
      separate MSI vectors - but also separate IRQs. As result,
      interrupts generated by different ports could be serviced on
      different CPUs rather than on a single one.
      
      In cases when number of allocated MSIs is less than requested
      the Sharing Last MSI mode does not get used, no matter
      implemented in hardware or not. Instead, the driver assumes the
      advantage of multiple MSIs is negated and falls back to the
      single MSI mode as if MRSM bit was set (some Intel chips
      implement this strategy anyway - MRSM bit gets set even if the
      number of allocated MSIs exceeds the number of implemented ports).
      Signed-off-by: NAlexander Gordeev <agordeev@redhat.com>
      Acked-by: NJeff Garzik <jgarzik@redhat.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Cc: Yinghai Lu <yinghai@kernel.org>
      Cc: Matthew Wilcox <willy@linux.intel.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Link: http://lkml.kernel.org/r/15bf7ee314dd55f21ec7d2a01c47613cd8190a7c.1353324359.git.agordeev@redhat.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
      5ca72c4f
  22. 15 1月, 2013 1 次提交
  23. 13 9月, 2012 3 次提交
  24. 18 8月, 2012 1 次提交
  25. 26 7月, 2012 3 次提交
  26. 04 5月, 2012 1 次提交
  27. 14 3月, 2012 2 次提交
  28. 09 1月, 2012 1 次提交
  29. 09 11月, 2011 1 次提交
  30. 24 7月, 2011 5 次提交