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  1. 10 7月, 2014 1 次提交
  3. 05 7月, 2014 1 次提交
  5. 01 7月, 2014 3 次提交
    • T
      ARM: mvebu: fix cpuidle implementation to work on big-endian systems · 6509dc74
      由 Thomas Petazzoni 提交于 
      On Marvell Armada XP, when a CPU comes back from deep idle state of
cpuidle, it restarts its execution at armada_370_xp_cpu_resume(),
which puts back the CPU into the coherency, and then calls the generic
cpu_resume() function.

While this works on little-endian configurations, it doesn't work on
big-endian configurations because the CPU restarts in little-endian,
and therefore must be switched back to big-endian to operate
properly. To achieve this, a 'setend be' instruction must be executed
in big-endian configurations. However, the ARM_BE8() macro that is
used to implement nice compile-time conditional for ARM LE vs. ARM BE8
is not easily usable in inline assembly.

Therefore, this patch moves the armada_370_xp_cpu_resume() C function,
which was anyway just a block of inline assembly, into a proper
pmsu_ll.S file, and adds the appropriate ARM_BE8(setend be)
instruction.

Without this patch, an Armada XP big endian configuration with cpuidle
enabled fails to boot, as it hangs as soon as one of the CPU hits the
deep idle state.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404130165-3593-1-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
      6509dc74
    • T
      ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup · 01178890
      由 Thomas Petazzoni 提交于 
      Commit 497a9230 ("ARM: mvebu:
implement L2/PCIe deadlock workaround") introduced some logic in
coherency.c to adjust the PL310 cache controller Device Tree node of
Armada 375 and Armada 38x platform to include the 'arm,io-coherent'
property if the system is running with hardware I/O coherency enabled.

However, with the L2CC driver cleanup done by Russell King, the
initialization of the L2CC driver has been moved earlier, and is now
part of the init_IRQ() ARM function in
arch/arm/kernel/irq.c. Therefore, calling coherency_init() in
->init_time() is now too late, as the Device Tree property gets added
too late (after the L2CC driver has been initialized).

In order to fix this, this commit removes the ->init_time() callback
use in board-v7.c and replaces it with an ->init_irq() callback. We
therefore no longer use the default ->init_irq() callback, but we now
use the default ->init_time() callback.

In this newly introduced ->init_irq() callback, we call irqchip_init()
which is the default behavior when ->init_irq() isn't defined, and
then do the initialization related to the coherency: SCU, coherency
fabric, and mvebu-mbus (which is needed to start secondary CPUs).
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-4-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
      01178890
    • T
      ARM: mvebu: move Armada 375 external abort logic as a quirk · 752ef800
      由 Thomas Petazzoni 提交于 
      In preparation to a small re-organization of the initialization
sequence in board-v7.c, this commit moves the registration of the
custom external abort handler on Armada 375 later in the boot
sequence, and makes it more similar to the other quirks that we
already have. There is indeed no need to register this abort handler
particularly early, it simply needs to be registered before switching
to userspace.

In addition to this, this commit makes the registration of the custom
abort handler conditional on Armada 375 Z1, because Armada 375 A0 and
later iterations are not affected by the issue.

This commit was tested on both Armada 375 Z1 and Armada 375 A0
platforms.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-3-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
      752ef800
  7. 29 6月, 2014 6 次提交
  9. 27 6月, 2014 1 次提交
    • O
      ARM: bcm: Fix bcm and multi_v7 defconfigs · bfda90cb
      由 Olof Johansson 提交于 
      BCM (Kona/capri platform) has regressed in two ways on this release. First,
bcm_defconfig no longer selected the appropriate MMC driver options due to
changes in dependencies. Secondly, the new MFD and regulator drivers were not
enabled on multi_v7_defconfig, so that caused the system to fail probing MMC
there.

Fix by enabling the new options as needed.

Cc: Matt Porter <matt.porter@linaro.org>
Cc: Christian Daudt <bcm@fixthebug.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>
      bfda90cb
  11. 26 6月, 2014 1 次提交
  13. 25 6月, 2014 4 次提交
  15. 24 6月, 2014 3 次提交
  17. 21 6月, 2014 7 次提交
  19. 20 6月, 2014 3 次提交
  21. 19 6月, 2014 3 次提交
    • R
      ARM: perf: fix compiler warning with gcc 4.6.4 (and tidy code) · 6a78371a
      由 Russell King 提交于 
      GCC 4.6.4 spits out the following warning when building perf_event_v7.c:

arch/arm/kernel/perf_event_v7.c: In function 'krait_pmu_get_event_idx':
arch/arm/kernel/perf_event_v7.c:1927:6: warning: 'bit' may be used uninitialized in this function

While upgrading the version of gcc may solve this, the code can also be
organised to be more efficient by not carrying more local variables than
is necessary across the armv7pmu_get_event_idx function call.  If we set
'bit' to -1 (which is invalid for clear_bit) we can use that as an
indication whether we need to clear a bit after this function.
Acked-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      6a78371a
    • R
      ARM: l2c: fix dependencies on PL310 errata symbols · a641f3a6
      由 Russell King 提交于 
      A number of configurations spit out warnings similar to:

warning: (SOC_IMX6 && SOC_VF610 && ARCH_OMAP4) selects PL310_ERRATA_588369 which has unmet direct dependencies (CACHE_L2X0)
warning: (SOC_IMX6 && SOC_VF610 && ARCH_OMAP4) selects PL310_ERRATA_727915 which has unmet direct dependencies (CACHE_L2X0)

Clean up the dependencies here:
* PL310 symbols should only be selected when CACHE_L2X0 is enabled.
* Since the cache-l2x0 code detects PL310 presence at runtime, and we will
  eventually get rid of CACHE_PL310, surround these errata options with an
  if CACHE_L2X0 conditional rather than repeating the dependency against
  each.
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      a641f3a6
    • L
      ARM: stih41x: Rename stih416-b2020-revE.dts to stih416-b2020e.dts · 88a1c67f
      由 Lee Jones 提交于 
      Two reasons for this rename.  Firstly, it removes the camel case
convention which isn't used by any other platform and secondly it
matches the naming convention for the internal kernel, which can
become annoying when flipping between the two.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
      88a1c67f
  23. 18 6月, 2014 3 次提交
  25. 17 6月, 2014 4 次提交