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  1. 24 11月, 2016 1 次提交
  3. 17 11月, 2016 1 次提交
  5. 16 11月, 2016 2 次提交
  7. 11 11月, 2016 11 次提交
  9. 10 11月, 2016 2 次提交
  11. 09 11月, 2016 5 次提交
    • L
      drm/imx: disable planes before DC · 5ced937b
      由 Lucas Stach 提交于 
      If the DC clock is disabled before the attached IDMACs are properly
stopped the IDMACs may hang the IPU or even the whole system.

Make sure the IDMACs are in safe state by disabling the planes before
removal of the DC clock.

Also set the atomic parameter to false to stop calling the atomic_begin
hook, which does nothing useful as we immediately afterwards turn off
vblank interrupts and possibly send the pending vblank event.

Fixes: 33f14235 (drm/imx: atomic phase 1: Use transitional atomic
                     CRTC and plane helpers)
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
      5ced937b
    • S
      drm/fsl-dcu: disable planes before disabling CRTC · 3d6f3710
      由 Stefan Agner 提交于 
      After disabling and reenabling the CRTC the DCU sometimes got stuck
displaying the whole screen with a solid color. Disabling and
reenabling the CRTC did not recover from the situation. This was
often reproducable by just restarting the X-Server.

The disabling sequence is not explicitly documented. But it turns
out that disabling the planes before disabling the CRTC seems to
prevent the above situation from happening.

Use the callback ->atomic_disable instead of ->disable which allows
to use the drm_atomic_helper_disable_planes_on_crtc() helper to
disable planes before disabling the controller.
Signed-off-by: NStefan Agner <stefan@agner.ch>
      3d6f3710
    • S
      drm/fsl-dcu: update all registers on flush · 93daeeca
      由 Stefan Agner 提交于 
      Use the UPDATE_MODE READREG bit to initiate a register transfer
on flush. This makes sure that we flush all registers only once
for all planes.
Signed-off-by: NStefan Agner <stefan@agner.ch>
      93daeeca
    • S
      drm/fsl-dcu: do not update when modifying irq registers · 34a515d2
      由 Stefan Agner 提交于 
      The IRQ status and mask registers are not "double buffered" according
to the reference manual. Hence, there is no extra transfer/update
write needed when modifying these registers.
Signed-off-by: NStefan Agner <stefan@agner.ch>
      34a515d2
    • A
      drm/amd/powerplay: return false instead of -EINVAL · f20024d8
      由 Andrew Shadura 提交于 
      Returning -EINVAL from a bool-returning function
phm_check_smc_update_required_for_display_configuration has an unexpected
effect of returning true, which is probably not what was intended.
Replace -EINVAL by false.

The only place this function is called from is
psm_adjust_power_state_dynamic in
drivers/gpu/drm/amd/powerplay/eventmgr/psm.c:106:

	if (!equal || phm_check_smc_update_required_for_display_configuration(hwmgr)) {
		phm_apply_state_adjust_rules(hwmgr, requested, pcurrent);
		phm_set_power_state(hwmgr, &pcurrent->hardware, &requested->hardware);
		hwmgr->current_ps = requested;
	}

It seems to expect a boolean value here.

This issue has been found using the following Coccinelle semantic patch
written by Peter Senna Tschudin:
<smpl>
@@
identifier f;
constant C;
typedef bool;
@@
bool f (...){
<+...
* return -C;
...+>
}
</smpl>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAndrew Shadura <andrew.shadura@collabora.co.uk>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      f20024d8
  13. 08 11月, 2016 8 次提交
  15. 07 11月, 2016 2 次提交
  17. 06 11月, 2016 8 次提交