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  1. 03 4月, 2014 2 次提交
    • M
      s390/mm,tlb: optimize TLB flushing for zEC12 · 1b948d6c
      由 Martin Schwidefsky 提交于 
      The zEC12 machines introduced the local-clearing control for the IDTE
and IPTE instruction. If the control is set only the TLB of the local
CPU is cleared of entries, either all entries of a single address space
for IDTE, or the entry for a single page-table entry for IPTE.
Without the local-clearing control the TLB flush is broadcasted to all
CPUs in the configuration, which is expensive.

The reset of the bit mask of the CPUs that need flushing after a
non-local IDTE is tricky. As TLB entries for an address space remain
in the TLB even if the address space is detached a new bit field is
required to keep track of attached CPUs vs. CPUs in the need of a
flush. After a non-local flush with IDTE the bit-field of attached CPUs
is copied to the bit-field of CPUs in need of a flush. The ordering
of operations on cpu_attach_mask, attach_count and mm_cpumask(mm) is
such that an underindication in mm_cpumask(mm) is prevented but an
overindication in mm_cpumask(mm) is possible.
Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
      1b948d6c
    • M
      s390/mm,tlb: safeguard against speculative TLB creation · 02a8f3ab
      由 Martin Schwidefsky 提交于 
      The principles of operations states that the CPU is allowed to create
TLB entries for an address space anytime while an ASCE is loaded to
the control register. This is true even if the CPU is running in the
kernel and the user address space is not (actively) accessed.

In theory this can affect two aspects of the TLB flush logic.
For full-mm flushes the ASCE of the dying process is still attached.
The approach to flush first with IDTE and then just free all page
tables can in theory lead to stale TLB entries. Use the batched
free of page tables for the full-mm flushes as well.

For operations that can have a stale ASCE in the control register,
e.g. a delayed update_user_asce in switch_mm, load the kernel ASCE
to prevent invalid TLBs from being created.
Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
      02a8f3ab
  3. 21 3月, 2014 2 次提交
  5. 21 2月, 2014 3 次提交
  7. 16 1月, 2014 1 次提交
  9. 15 11月, 2013 2 次提交
  11. 04 11月, 2013 1 次提交
    • M
      s390/mm,tlb: correct tlb flush on page table upgrade · 10607864
      由 Martin Schwidefsky 提交于 
      The IDTE instruction used to flush TLB entries for a specific address
space uses the address-space-control element (ASCE) to identify
affected TLB entries. The upgrade of a page table adds a new top
level page table which changes the ASCE. The TLB entries associated
with the old ASCE need to be flushed and the ASCE for the address space
needs to be replaced synchronously on all CPUs which currently use it.
The concept of a lazy ASCE update with an exception handler is broken.
Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
      10607864
  13. 31 10月, 2013 1 次提交
  15. 24 10月, 2013 1 次提交
  17. 07 9月, 2013 2 次提交
  19. 29 8月, 2013 1 次提交
    • M
      s390/mm: implement software referenced bits · 0944fe3f
      由 Martin Schwidefsky 提交于 
      The last remaining use for the storage key of the s390 architecture
is reference counting. The alternative is to make page table entries
invalid while they are old. On access the fault handler marks the
pte/pmd as young which makes the pte/pmd valid if the access rights
allow read access. The pte/pmd invalidations required for software
managed reference bits cost a bit of performance, on the other hand
the RRBE/RRBM instructions to read and reset the referenced bits are
quite expensive as well.
Reviewed-by: NGerald Schaefer <gerald.schaefer@de.ibm.com>
Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
      0944fe3f
  21. 22 8月, 2013 2 次提交
  23. 29 7月, 2013 2 次提交
  25. 27 6月, 2013 1 次提交
  27. 20 6月, 2013 1 次提交
  29. 17 6月, 2013 1 次提交
  31. 31 5月, 2013 1 次提交
  33. 21 5月, 2013 2 次提交
  35. 15 5月, 2013 1 次提交
  37. 03 5月, 2013 1 次提交
  39. 23 4月, 2013 2 次提交
  41. 08 3月, 2013 1 次提交
  43. 23 11月, 2012 1 次提交
  45. 09 10月, 2012 4 次提交
  47. 26 9月, 2012 2 次提交
  49. 30 7月, 2012 1 次提交
  51. 26 7月, 2012 1 次提交