1. 15 5月, 2012 1 次提交
  2. 10 4月, 2012 1 次提交
  3. 13 2月, 2012 1 次提交
  4. 19 10月, 2011 1 次提交
    • A
      EHCI: workaround for MosChip controller bug · 68aa95d5
      Alan Stern 提交于
      This patch (as1489) works around a hardware bug in MosChip EHCI
      controllers.  Evidently when one of these controllers increments the
      frame-index register, it changes the three low-order bits (the
      microframe counter) before changing the higher order bits (the frame
      counter).  If the register is read at just the wrong time, the value
      obtained is too low by 8.
      
      When the appropriate quirk flag is set, we work around this problem by
      reading the frame-index register a second time if the first value's
      three low-order bits are all 0.  This gives the hardware a chance to
      finish updating the register, yielding the correct value.
      Signed-off-by: NAlan Stern <stern@rowland.harvard.edu>
      Tested-by: NJason N Pitt <jpitt@fhcrc.org>
      CC: stable <stable@vger.kernel.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      68aa95d5
  5. 23 8月, 2011 1 次提交
    • A
      USB: EHCI: remove usages of hcd->state · e8799906
      Alan Stern 提交于
      This patch (as1483) improves the ehci-hcd driver family by getting rid
      of the reliance on the hcd->state variable.  It has no clear owner and
      it isn't protected by the usual HCD locks.  In its place, the patch
      adds a new, private ehci->rh_state field to record the state of the
      root hub.
      
      Along the way, the patch removes a couple of lines containing
      redundant assignments to the state variable.  Also, the QUIESCING
      state simply gets changed to the RUNNING state, because the driver
      doesn't make any distinction between them.
      Signed-off-by: NAlan Stern <stern@rowland.harvard.edu>
      Acked-by: NJingoo Han <jg1.han@samsung.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      e8799906
  6. 20 7月, 2011 1 次提交
    • A
      EHCI: fix direction handling for interrupt data toggles · e04f5f7e
      Alan Stern 提交于
      This patch (as1480) fixes a rather obscure bug in ehci-hcd.  The
      qh_update() routine needs to know the number and direction of the
      endpoint corresponding to its QH argument.  The number can be taken
      directly from the QH data structure, but the direction isn't stored
      there.  The direction is taken instead from the first qTD linked to
      the QH.
      
      However, it turns out that for interrupt transfers, qh_update() gets
      called before the qTDs are linked to the QH.  As a result, qh_update()
      computes a bogus direction value, which messes up the endpoint toggle
      handling.  Under the right combination of circumstances this causes
      usb_reset_endpoint() not to work correctly, which causes packets to be
      dropped and communications to fail.
      
      Now, it's silly for the QH structure not to have direct access to all
      the descriptor information for the corresponding endpoint.  Ultimately
      it may get a pointer to the usb_host_endpoint structure; for now,
      adding a copy of the direction flag solves the immediate problem.
      
      This allows the Spyder2 color-calibration system (a low-speed USB
      device that sends all its interrupt data packets with the toggle set
      to 0 and hance requires constant use of usb_reset_endpoint) to work
      when connected through a high-speed hub.  Thanks to Graeme Gill for
      supplying the hardware that allowed me to track down this bug.
      Signed-off-by: NAlan Stern <stern@rowland.harvard.edu>
      Reported-by: NGraeme Gill <graeme@argyllcms.com>
      CC: <stable@kernel.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      e04f5f7e
  7. 09 7月, 2011 2 次提交
    • A
      USB: EHCI: go back to using the system clock for QH unlinks · 004c1968
      Alan Stern 提交于
      This patch (as1477) fixes a problem affecting a few types of EHCI
      controller.  Contrary to what one might expect, these controllers
      automatically stop their internal frame counter when no ports are
      enabled.  Since ehci-hcd currently relies on the frame counter for
      determining when it should unlink QHs from the async schedule, those
      controllers run into trouble: The frame counter stops and the QHs
      never get unlinked.
      
      Some systems have also experienced other problems traced back to
      commit b9638011 (USB: ehci-hcd unlink
      speedups), which made the original switch from using the system clock
      to using the frame counter.  It never became clear what the reason was
      for these problems, but evidently it is related to use of the frame
      counter.
      
      To fix all these problems, this patch more or less reverts that commit
      and goes back to using the system clock.  But this can't be done
      cleanly because other changes have since been made to the scan_async()
      subroutine.  One of these changes involved the tricky logic that tries
      to avoid rescanning QHs that have already been seen when the scanning
      loop is restarted, which happens whenever an URB is given back.
      Switching back to clock-based unlinks would make this logic even more
      complicated.
      
      Therefore the new code doesn't rescan the entire async list whenever a
      giveback occurs.  Instead it rescans only the current QH and continues
      on from there.  This requires the use of a separate pointer to keep
      track of the next QH to scan, since the current QH may be unlinked
      while the scanning is in progress.  That new pointer must be global,
      so that it can be adjusted forward whenever the _next_ QH gets
      unlinked.  (uhci-hcd uses this same trick.)
      
      Simplification of the scanning loop removes a level of indentation,
      which accounts for the size of the patch.  The amount of code changed
      is relatively small, and it isn't exactly a reversion of the
      b9638011 commit.
      
      This fixes Bugzilla #32432.
      Signed-off-by: NAlan Stern <stern@rowland.harvard.edu>
      CC: <stable@kernel.org>
      Tested-by: NMatej Kenda <matejken@gmail.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      004c1968
    • K
      USB: EHCI: Allow users to override 80% max periodic bandwidth · cc62a7eb
      Kirill Smelkov 提交于
      There are cases, when 80% max isochronous bandwidth is too limiting.
      
      For example I have two USB video capture cards which stream uncompressed
      video, and to stream full NTSC + PAL videos we'd need
      
          NTSC 640x480 YUV422 @30fps      ~17.6 MB/s
          PAL  720x576 YUV422 @25fps      ~19.7 MB/s
      
      isoc bandwidth.
      
      Now, due to limited alt settings in capture devices NTSC one ends up
      streaming with max_pkt_size=2688  and  PAL with max_pkt_size=2892, both
      with interval=1. In terms of microframe time allocation this gives
      
          NTSC    ~53us
          PAL     ~57us
      
      and together
      
          ~110us  >  100us == 80% of 125us uframe time.
      
      So those two devices can't work together simultaneously because the'd
      over allocate isochronous bandwidth.
      
      80% seemed a bit arbitrary to me, and I've tried to raise it to 90% and
      both devices started to work together, so I though sometimes it would be
      a good idea for users to override hardcoded default of max 80% isoc
      bandwidth.
      
      After all, isn't it a user who should decide how to load the bus? If I
      can live with 10% or even 5% bulk bandwidth that should be ok. I'm a USB
      newcomer, but that 80% set in stone by USB 2.0 specification seems to be
      chosen pretty arbitrary to me, just to serve as a reasonable default.
      
      NOTE 1
      ~~~~~~
      
      for two streams with max_pkt_size=3072 (worst case) both time
      allocation would be 60us+60us=120us which is 96% periodic bandwidth
      leaving 4% for bulk and control.  Alan Stern suggested that bulk then
      would be problematic (less than 300*8 bittimes left per microframe), but
      I think that is still enough for control traffic.
      
      NOTE 2
      ~~~~~~
      
      Sarah Sharp expressed concern that maxing out periodic bandwidth
      could lead to vendor-specific hardware bugs on host controllers, because
      
      > It's entirely possible that you'll run into
      > vendor-specific bugs if you try to pack the schedule with isochronous
      > transfers.  I don't think any hardware designer would seriously test or
      > validate their hardware with a schedule that is basically a violation of
      > the USB bus spec (more than 80% for periodic transfers).
      
      So far I've only tested this patch on my HP Mini 5103 with N10 chipset
      
          kirr@mini:~$ lspci
          00:00.0 Host bridge: Intel Corporation N10 Family DMI Bridge
          00:02.0 VGA compatible controller: Intel Corporation N10 Family Integrated Graphics Controller
          00:02.1 Display controller: Intel Corporation N10 Family Integrated Graphics Controller
          00:1b.0 Audio device: Intel Corporation N10/ICH 7 Family High Definition Audio Controller (rev 02)
          00:1c.0 PCI bridge: Intel Corporation N10/ICH 7 Family PCI Express Port 1 (rev 02)
          00:1c.3 PCI bridge: Intel Corporation N10/ICH 7 Family PCI Express Port 4 (rev 02)
          00:1d.0 USB Controller: Intel Corporation N10/ICH 7 Family USB UHCI Controller #1 (rev 02)
          00:1d.1 USB Controller: Intel Corporation N10/ICH 7 Family USB UHCI Controller #2 (rev 02)
          00:1d.2 USB Controller: Intel Corporation N10/ICH 7 Family USB UHCI Controller #3 (rev 02)
          00:1d.3 USB Controller: Intel Corporation N10/ICH 7 Family USB UHCI Controller #4 (rev 02)
          00:1d.7 USB Controller: Intel Corporation N10/ICH 7 Family USB2 EHCI Controller (rev 02)
          00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev e2)
          00:1f.0 ISA bridge: Intel Corporation NM10 Family LPC Controller (rev 02)
          00:1f.2 SATA controller: Intel Corporation N10/ICH7 Family SATA AHCI Controller (rev 02)
          01:00.0 Network controller: Broadcom Corporation BCM4313 802.11b/g/n Wireless LAN Controller (rev 01)
          02:00.0 Ethernet controller: Marvell Technology Group Ltd. 88E8059 PCI-E Gigabit Ethernet Controller (rev 11)
      
      and the system works stable with 110us/uframe (~88%) isoc bandwith allocated for
      above-mentioned isochronous transfers.
      
      NOTE 3
      ~~~~~~
      
      This feature is off by default. I mean max periodic bandwidth is set to
      100us/uframe by default exactly as it was before the patch. So only those of us
      who need the extreme settings are taking the risk - normal users who do not
      alter uframe_periodic_max sysfs attribute should not see any change at all.
      
      NOTE 4
      ~~~~~~
      
      I've tried to update documentation in Documentation/ABI/ thoroughly, but
      only "TBD" was put into Documentation/usb/ehci.txt -- the text there seems
      to be outdated and much needing refreshing, before it could be amended.
      
      Cc: Sarah Sharp <sarah.a.sharp@linux.intel.com>
      Signed-off-by: NKirill Smelkov <kirr@mns.spb.ru>
      Acked-by: NAlan Stern <stern@rowland.harvard.edu>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      cc62a7eb
  8. 20 5月, 2011 1 次提交
  9. 18 5月, 2011 1 次提交
    • A
      EHCI: don't rescan interrupt QHs needlessly · 1e12c910
      Alan Stern 提交于
      This patch (as1466) speeds up processing of ehci-hcd's periodic list.
      The existing code will pointlessly rescan an interrupt endpoint queue
      each time it encounters the queue's QH in the periodic list, which can
      happen quite a few times if the endpoint's period is low.  On some
      embedded systems, this useless overhead can waste so much time that
      the driver falls hopelessly behind and loses events.
      
      The patch introduces a "periodic_stamp" variable, which gets
      incremented each time scan_periodic() runs and each time the scan
      advances to a new frame.  If the corresponding stamp in an interrupt
      QH is equal to the current periodic_stamp, we assume the QH has
      already been scanned and skip over it.  Otherwise we scan the QH as
      usual, and if none of its URBs have completed then we store the
      current periodic_stamp in the QH's stamp, preventing it from being
      scanned again.
      Signed-off-by: NAlan Stern <stern@rowland.harvard.edu>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      1e12c910
  10. 04 5月, 2011 2 次提交
  11. 03 5月, 2011 1 次提交
  12. 14 4月, 2011 1 次提交
    • G
      USB: ehci: add workaround for Synopsys HC bug · 2f7ac6c1
      Gabor Juhos 提交于
      A Synopsys USB core used in various SoCs has a bug which might cause
      that the host controller not issuing ping.
      
      When software uses the Doorbell mechanism to remove queue heads, the
      host controller still has references to the removed queue head even
      after indicating an Interrupt on Async Advance. This happens if the last
      executed queue head's Next Link queue head is removed.
      
      Consequences of the defect:
      The Host controller fetches the removed queue head, using memory that
      would otherwise be deallocated.This results in incorrect transactions on
      both the USB and system memory. This may result in undefined behavior.
      
      Workarounds:
      
      1) If no queue head is active (no Status field's Active bit is set)
      after removing the queue heads, the software can write one of the valid
      queue head addresses to the ASYNCLISTADDR register and deallocate the
      removed queue head's memory after 2 microframes.
      
      If one or more of the queue heads is active (the Active bit is set in
      the Status field) after removing the queue heads, the software can delay
      memory deallocation after time X, where X is the time required for the
      Host Controller to go through all the queue heads once. X varies with
      the number of queue heads and the time required to process periodic
      transactions: if more periodic transactions must be performed, the Host
      Controller has less time to process asynchronous transaction processing.
      
      2) Do not use the Doorbell mechanism to remove the queue heads. Disable
      the Asynchronous Schedule Enable bit instead.
      
      The bug has been discussed on the linux-usb-devel mailing-list
      four years ago, the original thread can be found here:
      http://www.mail-archive.com/linux-usb-devel@lists.sourceforge.net/msg45345.html
      
      This patch implements the first workaround as suggested by David Brownell.
      
      The built-in USB host controller of the Atheros AR7130/AR7141/AR7161 SoCs
      requires this to work properly.
      Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
      Acked-by: NAlan Stern <stern@rowland.harvard.edu>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      2f7ac6c1
  13. 31 3月, 2011 1 次提交
  14. 02 3月, 2011 1 次提交
    • A
      USB host: Move AMD PLL quirk to pci-quirks.c · ad93562b
      Andiry Xu 提交于
      This patch moves the AMD PLL quirk code in OHCI/EHCI driver to pci-quirks.c,
      and exports the functions to be used by xHCI driver later.
      
      AMD PLL quirk disable the optional PM feature inside specific
      SB700/SB800/Hudson-2/3 platforms under the following conditions:
      
      1. If an isochronous device is connected to OHCI/EHCI/xHCI port and is active;
      2. Optional PM feature that powers down the internal Bus PLL when the link is
         in low power state is enabled.
      
      Without AMD PLL quirk, USB isochronous stream may stutter or have breaks
      occasionally, which greatly impair the performance of audio/video streams.
      
      Currently AMD PLL quirk is implemented in OHCI and EHCI driver, and will be
      added to xHCI driver too. They are doing similar things actually, so move
      the quirk code to pci-quirks.c, which has several advantages:
      
      1. Remove duplicate defines and functions in OHCI/EHCI (and xHCI) driver and
         make them cleaner;
      2. AMD chipset information will be probed only once and then stored.
         Currently they're probed during every OHCI/EHCI initialization, move
         the detect code to pci-quirks.c saves the repeat detect cost;
      3. Build up synchronization among OHCI/EHCI/xHCI driver. In current
         code, every host controller enable/disable PLL only according to
         its own status, and may enable PLL while there is still isoc transfer on
         other HCs. Move the quirk to pci-quirks.c prevents this issue.
      Signed-off-by: NAndiry Xu <andiry.xu@amd.com>
      Cc: David Brownell <dbrownell@users.sourceforge.net>
      Cc: Alex He <alex.he@amd.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      ad93562b
  15. 18 2月, 2011 1 次提交
  16. 05 2月, 2011 1 次提交
    • A
      USB host: Move AMD PLL quirk to pci-quirks.c · b7d5b439
      Andiry Xu 提交于
      This patch moves the AMD PLL quirk code in OHCI/EHCI driver to pci-quirks.c,
      and exports the functions to be used by xHCI driver later.
      
      AMD PLL quirk disable the optional PM feature inside specific
      SB700/SB800/Hudson-2/3 platforms under the following conditions:
      
      1. If an isochronous device is connected to OHCI/EHCI/xHCI port and is active;
      2. Optional PM feature that powers down the internal Bus PLL when the link is
         in low power state is enabled.
      
      Without AMD PLL quirk, USB isochronous stream may stutter or have breaks
      occasionally, which greatly impair the performance of audio/video streams.
      
      Currently AMD PLL quirk is implemented in OHCI and EHCI driver, and will be
      added to xHCI driver too. They are doing similar things actually, so move
      the quirk code to pci-quirks.c, which has several advantages:
      
      1. Remove duplicate defines and functions in OHCI/EHCI (and xHCI) driver and
         make them cleaner;
      2. AMD chipset information will be probed only once and then stored.
         Currently they're probed during every OHCI/EHCI initialization, move
         the detect code to pci-quirks.c saves the repeat detect cost;
      3. Build up synchronization among OHCI/EHCI/xHCI driver. In current
         code, every host controller enable/disable PLL only according to
         its own status, and may enable PLL while there is still isoc transfer on
         other HCs. Move the quirk to pci-quirks.c prevents this issue.
      Signed-off-by: NAndiry Xu <andiry.xu@amd.com>
      Cc: David Brownell <dbrownell@users.sourceforge.net>
      Cc: Alex He <alex.he@amd.com>
      Acked-by: NAlan Stern <stern@rowland.harvard.edu>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      b7d5b439
  17. 11 12月, 2010 1 次提交
    • A
      USB: EHCI: ASPM quirk of ISOC on AMD SB800 · 05570297
      Alex He 提交于
      When ASPM PM Feature is enabled on UMI link, devices that use ISOC stream of
      data transfer may be exposed to longer latency causing less than optimal per-
      formance of the device. The longer latencies are normal and are due to link
      wake time coming out of low power state which happens frequently to save
      power when the link is not active.
      The following code will make exception for certain features of ASPM to be by
      passed and keep the logic normal state only when the ISOC device is connected
      and active. This change will allow the device to run at optimal performance
      yet minimize the impact on overall power savings.
      Signed-off-by: NAlex He <alex.he@amd.com>
      Acked-by: NDavid Brownell <dbrownell@users.sourceforge.net>
      Cc: stable <stable@kernel.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      05570297
  18. 17 11月, 2010 1 次提交
    • A
      USB: EHCI: AMD periodic frame list table quirk · 3d091a6f
      Andiry Xu 提交于
      On AMD SB700/SB800/Hudson-2/3 platforms, USB EHCI controller may read/write
      to memory space not allocated to USB controller if there is longer than
      normal latency on DMA read encountered. In this condition the exposure will
      be encountered only if the driver has following format of Periodic Frame
      List link pointer structure:
      
      For any idle periodic schedule, the Frame List link pointers that have the
      T-bit set to 1 intending to terminate the use of frame list link pointer
      as a physical memory pointer.
      
      Idle periodic schedule Frame List Link pointer shoule be in the following
      format to avoid the issue:
      
      Frame list link pointer should be always contains a valid pointer to a
      inactive QHead with T-bit set to 0.
      Signed-off-by: NAndiry Xu <andiry.xu@amd.com>
      Acked-by: NDavid Brownell <dbrownell@users.sourceforge.net>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      3d091a6f
  19. 11 8月, 2010 7 次提交
  20. 21 5月, 2010 2 次提交
    • A
      USB: EHCI: fix controller wakeup flag settings during suspend · 16032c4f
      Alan Stern 提交于
      This patch (as1380) fixes a bug in the wakeup settings for EHCI host
      controllers.  When the controller is suspended, if it isn't enabled
      for remote wakeup then we have to turn off all the port wakeup flags.
      Disabling PCI PME# isn't good enough, because some systems (Intel)
      evidently use alternate wakeup signalling paths.
      
      In addition, the patch improves the handling of the Intel Moorestown
      hardware by performing various power-up and power-down delays just
      once instead of once for each port (i.e., the delays are moved outside
      of the port loops).  This requires extra code, but the total delay
      time is reduced.
      
      There are also a few additional minor cleanups.
      Signed-off-by: NAlan Stern <stern@rowland.harvard.edu>
      Reported-by: NOndrej Zary <linux@rainbow-software.org>
      CC: Alek Du <alek.du@intel.com>
      CC: stable <stable@kernel.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      16032c4f
    • A
      USB: remove bogus USB_PORT_FEAT_*_SPEED symbols · 288ead45
      Alan Stern 提交于
      This patch (as1348) removes the bogus
      USB_PORT_FEAT_{HIGHSPEED,SUPERSPEED} symbols from ch11.h.  No such
      features are defined by the USB spec.  (There is a PORT_LOWSPEED
      feature, but the spec doesn't mention it except to say that host
      software should never use it.)  The speed indicators are port
      statuses, not port features.
      
      As a temporary workaround for the xhci-hcd driver, a fictional
      USB_PORT_STAT_SUPER_SPEED symbol is added.
      Signed-off-by: NAlan Stern <stern@rowland.harvard.edu>
      CC: Sarah Sharp <sarah.a.sharp@linux.intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      288ead45
  21. 23 4月, 2010 1 次提交
  22. 19 3月, 2010 1 次提交
  23. 01 12月, 2009 1 次提交
  24. 23 9月, 2009 4 次提交
    • A
      USB: EHCI: rescan the queue after an unlink · 3a44494e
      Alan Stern 提交于
      This patch (as1280) fixes an obscure bug in ehci-hcd's dequeuing logic
      for async URBs.  If a later URB is unlinked and the completion
      routine unlinks an earlier URB, then the earlier URB won't be given
      back in a timely manner because the endpoint queue isn't rescanned as
      it should be.
      
      Similar bugs occur if an endpoint is reset or a halt is cleared while
      a completion routine is running, because the subroutines don't test
      for the COMPLETING state.
      
      All these problems are solved by adding a new needs_rescan flag to the
      ehci_qh structure.  If the flag is set while scanning through an idle
      QH, the scan will be repeated.  If the QH isn't idle then an unlink
      cycle will be initiated, and the proper action will be taken when it
      becomes idle.
      
      Also, an unnecessary test is removed from qh_link_async(): That
      routine is never called if the QH's state isn't IDLE.
      Signed-off-by: NAlan Stern <stern@rowland.harvard.edu>
      CC: David Brownell <david-b@pacbell.net>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      3a44494e
    • A
      USB: EHCI: Add Intel Moorestown EHCI controller HOSTPCx extensions and support phy low power mode · 331ac6b2
      Alek Du 提交于
      The Intel Moorestown EHCI controller supports non-standard HOSTPCx register
      extension. This register controls the LPM behaviour and controls the behaviour
      of each USB port.
      Signed-off-by: NJacob Pan <jacob.jun.pan@intel.com>
      Signed-off-by: NAlek Du <alek.du@intel.com>
      Acked-by: NAlan Stern <stern@rowland.harvard.edu>
      Cc: David Brownell <dbrownell@users.sourceforge.net>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      
      331ac6b2
    • A
      USB: EHCI: split ehci_qh into hw and sw parts · 3807e26d
      Alek Du 提交于
      The ehci_qh structure merged hw and sw together which is not good:
      1. More and more items are being added into ehci_qh, the ehci_qh software
         part are unnecessary to be allocated in DMA qh_pool.
      2. If HCD has local SRAM, the sw part will consume it too, and it won't
         bring any benefit.
      3. For non-cache-coherence system, the entire ehci_qh is uncachable, actually
         we only need the hw part to be uncacheable. Spliting them will let the sw
         part to be cacheable.
      Signed-off-by: NAlek Du <alek.du@intel.com>
      Cc: David Brownell <dbrownell@users.sourceforge.net>
      CC: Alan Stern <stern@rowland.harvard.edu>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      3807e26d
    • A
      USB: EHCI: add need_io_watchdog flag to ehci_hcd · 403dbd36
      Alek Du 提交于
      Basically the io watchdog is only useful for those quirk HCDs. For most
      good ones, it only brings unnecessary wakeups.  At least, I know the
      Intel EHCI HCDs should turn off the flag.
      Signed-off-by: NAlek Du <alek.du@intel.com>
      Cc: David Brownell <dbrownell@users.sourceforge.net>
      Cc: Alan Stern <stern@rowland.harvard.edu>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      403dbd36
  25. 21 9月, 2009 1 次提交
  26. 13 7月, 2009 1 次提交
  27. 16 6月, 2009 1 次提交
  28. 25 3月, 2009 1 次提交