1. 16 7月, 2008 1 次提交
  2. 09 7月, 2008 2 次提交
  3. 16 6月, 2008 4 次提交
  4. 06 6月, 2008 2 次提交
  5. 12 5月, 2008 1 次提交
  6. 29 4月, 2008 8 次提交
  7. 08 4月, 2008 1 次提交
  8. 01 4月, 2008 1 次提交
  9. 12 3月, 2008 2 次提交
  10. 20 2月, 2008 3 次提交
    • T
      [MIPS] SB1: Fix CONFIG_SIBYTE_DMA_PAGEOPS build failure. · 345599ab
      Thiemo Seufer 提交于
      Fix type mismatch warnings for 64-bit kernel builds which trigger -Werror.
      The problem affects only SB-1 kernels with CONFIG_SIBYTE_DMA_PAGEOPS
      enabled.
      Signed-off-by: NThiemo Seufer <ths@networkno.de>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      345599ab
    • R
      [MIPS] Fix buggy invocations of kmap_coherent() · 9a74b3eb
      Ralf Baechle 提交于
      kmap_coherent will only work correctly if the page it is called on is
      not marked dirty.  If it's dirty the kernel address of the page should
      be used instead of a temporary mapping.
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      9a74b3eb
    • R
      [MIPS] Handle I-cache coherency in flush_cache_range() · 2eaa7ec2
      Ralf Baechle 提交于
      So far flush_cache_range() did't consider the I-cache largely because it
      did rarely ever matter to real world code.  This was working primarily
      because normally code and data are don't share the same pages - with the
      exception of MIPS16 code which uses address constants embedded between
      the code.   The following sequence of events may break the code:
      
       o MIPS16 executable being loaded
       o dynamic linker relocates the address constants embedded into the code:
       o   Uses mprotect(2) to make code pages PROT_READ|PROT_WRITE
       o   Performs the actual relocations by writing to the pages which likely
           are COW.  Because no PROT_EXEC is set I-cache coherence will not be
           considered.
       o   Uses mprotect(2) to switch code pages back to PROT_READ|PROT_EXEC.
           This results in a call to flush_cache_range() which also does not
           consider I-caches.
       o => executing the page just having been relocated may now result in the
         I-cache getting refilled with stale data from memory.
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      2eaa7ec2
  11. 03 2月, 2008 1 次提交
  12. 01 2月, 2008 1 次提交
    • T
      [MIPS] Split the micro-assembler from tlbex.c. · e30ec452
      Thiemo Seufer 提交于
      This patch moves the micro-assembler in a separate implementation, as
      it is useful for further run-time optimizations. The only change in
      behaviour is cutting down printk noise at kernel startup time.
      
      Checkpatch complains about macro parameters which aren't protected by
      parentheses. I believe this is a flaw in checkpatch, the paste operator
      used in those macros won't work with parenthesised parameters.
      Signed-off-by: NThiemo Seufer <ths@networkno.de>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      e30ec452
  13. 29 1月, 2008 11 次提交
  14. 12 1月, 2008 1 次提交
  15. 27 11月, 2007 1 次提交
    • R
      [MIPS] 64-bit Sibyte kernels need DMA32. · cce335ae
      Ralf Baechle 提交于
      Sibyte SOCs only have 32-bit PCI.  Due to the sparse use of the address
      space only the first 1GB of memory is mapped at physical addresses
      below 1GB.  If a system has more than 1GB of memory 32-bit DMA will
      not be able to reach all of it.
      
      For now this patch is good enough to keep Sibyte users happy but it seems
      eventually something like swiotlb will be needed for Sibyte.
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      cce335ae
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