1. 17 2月, 2016 2 次提交
  2. 19 11月, 2015 1 次提交
  3. 28 10月, 2015 1 次提交
  4. 23 10月, 2015 1 次提交
    • L
      amd-xgbe: Use wmb before updating current descriptor count · 20a41fba
      Lendacky, Thomas 提交于
      The code currently uses the lightweight dma_wmb barrier before updating
      the current descriptor count. Under heavy load, the Tx cleanup routine
      was seeing the updated current descriptor count before the updated
      descriptor information. As a result, the Tx descriptor was being cleaned
      up before it was used because it was not "owned" by the hardware yet,
      resulting in a Tx queue hang.
      
      Using the wmb barrier insures that the descriptor is updated before the
      descriptor counter preventing the Tx queue hang. For extra insurance,
      the Tx cleanup routine is changed to grab the current decriptor count on
      entry and uses that initial value in the processing loop rather than
      trying to chase the current value.
      Signed-off-by: NTom Lendacky <thomas.lendacky@amd.com>
      Tested-by: NChristoffer Dall <christoffer.dall@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      20a41fba
  5. 15 10月, 2015 1 次提交
  6. 05 10月, 2015 2 次提交
  7. 09 7月, 2015 1 次提交
  8. 07 6月, 2015 1 次提交
  9. 25 5月, 2015 1 次提交
  10. 16 5月, 2015 4 次提交
  11. 15 5月, 2015 1 次提交
  12. 10 4月, 2015 3 次提交
  13. 21 3月, 2015 5 次提交
  14. 28 2月, 2015 1 次提交
    • L
      amd-xgbe: Request IRQs only after driver is fully setup · c30e76a7
      Lendacky, Thomas 提交于
      It is possible that the hardware may not have been properly shutdown
      before this driver gets control, through use by firmware, for example.
      Until the driver is loaded, interrupts associated with the hardware
      could go pending. When the IRQs are requested napi support has not
      been initialized yet, but the ISR will get control and schedule napi
      processing resulting in a kernel panic because the poll routine has not
      been set.
      
      Adjust the code so that the driver is fully ready to handle and process
      interrupts as soon as the IRQs are requested. This involves requesting
      and freeing IRQs during start and stop processing and ordering the napi
      add and delete calls appropriately.
      
      Also adjust the powerup and powerdown routines to match the start and
      stop routines in regards to the ordering of tasks, including napi
      related calls.
      Signed-off-by: NTom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c30e76a7
  15. 08 2月, 2015 1 次提交
  16. 05 2月, 2015 2 次提交
  17. 17 1月, 2015 4 次提交
  18. 14 1月, 2015 1 次提交
  19. 10 12月, 2014 3 次提交
  20. 22 11月, 2014 4 次提交