1. 30 9月, 2015 2 次提交
    • T
      ALSA: firewire-digi00x: add data block processing layer · 163ae6f3
      Takashi Sakamoto 提交于
      Digi 002/003 family uses its own format for data blocks. The format is
      quite similar to AM824 in IEC 61883-6, while there're some differences:
      
       * The Valid Bit Length (VBL) code is always 0x40 in Multi-bit Linear Audio
         (MBLA) data channel.
       * The first data channel includes MIDI messages, against IEC 61883-6
         recommendation.
       * The Counter field is always zero in MIDI conformant data channel.
       * Sequence multiplexing in IEC 61883-6 is not applied to the MIDI
         conformant data channel.
       * PCM samples are scrambled in received AMDTP packets. We call the way
         as Double-Oh-Three (DOT). The algorithm was discovered by
         Robin Gareus and Damien Zammit in 2012.
      
      This commit adds data processing layer to satisfy these differences.
      
      There's a quirk about transmission mode for received packets. When this
      driver applies non-blocking mode to outgoing packets with isochronous
      channel 2 or more, after 15 to 20 seconds since playbacking, any PCM
      samples causes noisy sound on the device. With isochronous channel 0 or 1,
      this doesn't occur. As long as I investigated, this quirk is not observed
      when applying blocking mode to the received packets.
      
      This driver applies blocking mode to outgoing packets, while non-blocking
      mode to incoming packgets.
      Signed-off-by: NTakashi Sakamoto <o-takashi@sakamocchi.jp>
      Signed-off-by: NTakashi Iwai <tiwai@suse.de>
      163ae6f3
    • T
      ALSA: firewire-digi00x: add skeleton for Digi 002/003 family · 9edf723f
      Takashi Sakamoto 提交于
      This commit adds a new driver for Digidesign 002/003 family. This commit
      just creates/removes card instance according to bus event. More functions
      will be added in following commits.
      
      Digidesign 002/003 family consists of:
       * Agere FW802B for IEEE 1394 PHY layer
       * PDI 1394L40 for IEEE 1394 LINK layer and IEC 61883 interface
       * ALTERA ACEX EP1K50 for IEC 61883 layer and DSP controller
       * ADSP-21065L for signal processing
      
      [minor cleanup using skip_spaces() by tiwai]
      Signed-off-by: NTakashi Sakamoto <o-takashi@sakamocchi.jp>
      Signed-off-by: NTakashi Iwai <tiwai@suse.de>
      9edf723f