Add IO bank timing support for S3C2412/S3C2443.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

Update the mapping of the memory controler registers and
add the missing definitions of the register block for the
SSMC.

The register contents definitions can be found in the pl093
header.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

Currently map-base.h defines the main virtual address mappings made
for all the support S3C SoC series, but does not then define any base
for per-cpu mappings to be made from.

Add S3C_ADDR_CPU() macro to define an virtual address as an offset
from the last of the core mappings.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

Add core support for frequency scaling on the S3C2412 SoC.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

Add CPU frequency scalling support to the Simtec Osiris.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

Add entries to select the crystal to select for each different
supported board. This information is then available for anything
else requiring this, such as the CPUFreq PLL tables.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

Add PLL tables for the S3C2440.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

Add core support for frequency scaling on the S3C2440 SoC.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

Add PLL table for the S3C2410 SoC.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

Add core support for frequency scaling on the S3C2410 SoC.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

Add io-timing support for frequency scaling on the S3C2410 SoC.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

Add the S3C24XX to the main ARM CPUFreq Kconfig support list.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

Add ARCH_HAS_CPUFREQ so that each machine config can select
it if they have CPUFREQ driver support. This means that the
CPUFREQ specific area does not need the if statement updating
each time a new machine is added.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

Move the structure s3c_cpufreq_config from cpu-freq.h to the
less advertised cpu-freq-core.h as it is not needed by anything
outside the core drivers.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

Update arch/arm/plat-s3c/include/plat/cpu-freq.h to include kerneldoc
style documentation.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

Add the core of the support for enabling the CPUFreq driver on
all S3C24XX based systems.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

Add definitions and an accessor macro to deal with
reading bus information from S3C2410_BWSCON for any
given numbered bank.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

The value of armclk_mask needs to be inverted for use as a mask on
the register value when updating ARM_RATIO.

This is critical for cpufreq support, without it attempts to scale
the frequency of the core trash pretty much the entire clock tree.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

If the requested clock is faster than the parent clock then the
parent clock is the closest we can get to the request so we need
to return that instead of the requested clock.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

In the s3c_gpiolib_getchip implementation for s3c24xx the check whether a pin is
in the gpio banks range is reversed. Thus the function returns NULL for valid
pins and the gpio chip if its not valid.

As a result gpio states are not saved/restored properly during suspend/resume.
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

This functionality is needed to kmap_atomic() highmem pages that may
potentially have or are about to set up other mappings with
non-standard caching attributes.
Signed-off-by: NThomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Those definitions are already provided by asm-generic
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: NPaul Mundt <lethal@linux-sh.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

mm: Pass virtual address to [__]p{te,ud,md}_free_tlb()

Upcoming paches to support the new 64-bit "BookE" powerpc architecture
will need to have the virtual address corresponding to PTE page when
freeing it, due to the way the HW table walker works.

Basically, the TLB can be loaded with "large" pages that cover the whole
virtual space (well, sort-of, half of it actually) represented by a PTE
page, and which contain an "indirect" bit indicating that this TLB entry
RPN points to an array of PTEs from which the TLB can then create direct
entries. Thus, in order to invalidate those when PTE pages are deleted,
we need the virtual address to pass to tlbilx or tlbivax instructions.

The old trick of sticking it somewhere in the PTE page struct page sucks
too much, the address is almost readily available in all call sites and
almost everybody implemets these as macros, so we may as well add the
argument everywhere. I added it to the pmd and pud variants for consistency.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: David Howells <dhowells@redhat.com> [MN10300 & FRV]
Acked-by: NNick Piggin <npiggin@suse.de>
Acked-by: Martin Schwidefsky <schwidefsky@de.ibm.com> [s390]
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Reviewed the Makefile on request by Michal and this is the resulting changes.

o Use ':=' for assignmnet so we do not re-evaluate for each use
o Use $(shell echo xxx) to remove ""
o Replaced CFLAGS_KERNEL with KBUILD_CFLAGS
  The settings are equally relevant for modules and the linked kernel
o Dropped LDFLAGS_BLOB - it is no longer used
o Refactored assignmnets to libs-y and core-y
o Use MMU for the MMU specific extension. "MMUEXT" was hurting my eyes
  and I did not wanted it spread to m68k
Signed-off-by: NSam Ravnborg <sam@ravnborg.org>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Signed-off-by: NMichal Simek <monstr@monstr.eu>

For example reiserfs use this relocation type.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

New reloc type R_MICROBLAZE_32_PCREL_LO requires a null handler (no work to do).

Remove legacy hack for broken linker pre gcc-4.1.1, that required us to extract
an offset from the code, add it to the addend, then rewrite the instruction.

Fixup the invalid reloc type error output.

Boot tested with the xilinx_emaclite ethernet driver.
Signed-off-by: NJohn Williams <john.williams@petalogix.com>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

The ipc system call is now unused in microblaze,
as the system call table points directly to the
indidual system calls for IPC.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

This patch add support for cases where load/store instruction
in put/get_user macro gets unaligned pointer to data and this
address is not valid. I prevent all cases which can failed.
I had to disable first stage of unaligned handler which is used
only for noMMU kernel and the whole work is done when interrupt
is enabled.
You have enable HW support for detect unaligned access in Microblaze.

This patch fixed three LTP tests:
getpeername01, getsockname01, socketpair01
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Signed-off-by: NMichal Simek <monstr@monstr.eu>

Calling fixup when we are in kernel mode. This
prevent fault for copy_to/from_user. This fault
was find thanks to writev01/03/04 LTP tests.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

We need to define _PAGE_FILE macro and change pte
functions. Microblaze use the same MMU as PowerPC
that's why we define _PAGE_FILE in the same style.
This change fixed remap_file_pages01 LTP test.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

For 64bits arguments gcc caused that put_user macro
works with wrong value because of optimalization.
Adding volatile caused that gcc not optimized it.

It is possible to use (as Blackfin do) two put_user
macros with 32bits arguments but there is one more
instruction which is due to duplication zero return
value which is called put_user_asm macro.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

It is necessary to zeroed r7 when r7 points to bad
dtb - this caused that we have correct messages
about compiled-in dtb or passing via r7
Signed-off-by: NMichal Simek <monstr@monstr.eu>

I can't clear r7 because if I do it I lose information
where DTB come from.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Print accurate message about place where FDT blob is.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

If r7 is zero at kernel boot, or does not point to a valid DTB, then
we fall back to a DTB (assumed to be) linked statically in the kernel, instead
of blindly copying bogus cruft into the kernel DTB memory region
Signed-off-by: NJohn Williams <john.williams@petalogix.com>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Remove duplicated #include('s) in
  arch/microblaze/include/asm/io.h
Signed-off-by: NHuang Weiyi <weiyi.huang@gmail.com>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

This fix remove bug which we had till now in all
Microblaze MMU code. Primary tested on mmap01 LTP test.
We forget to flush invalid tlb which were changed - we
used them and there were wrong old data which wasn't correct.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

The combination of noexec=on and a clock_gettime call with clock id
CLOCK_THREAD_CPUTIME_ID is broken. The vdso code switches to the
access register mode to get access to the per-cpu data structure to
execute the magic ectg instruction. After the ectg instruction the
code always switches back to the primary mode but for noexec=on the
correct mode is the secondary mode. The effect of the bug is that the
user space program looses the access to all mappings without PROT_EXEC,
e.g. the stack. The problem is fixed by restoring the mode that has
been active before the switch to the access register mode.
Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>