Generalize assembler reset routine to allow use on several at91sam9 chips.
This patch replace double definitions of SDRAM controller registers and RSTC
registers with use of classical header files.

For this rework, we remove the not needed icache flush as it is already
done in the calling function: arm_machine_restart().

Rename at91sam9g20_reset.S to generalize to several chips.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Preparing next patch with longer names
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

If the SDRAM is not cleanly shutdown before reset it can be left driving
the bus, which then stops the bootloader booting from NAND.
Signed-off-by: NPeter Horton <phorton@bitbox.co.uk>
[nicolas.ferre@atmel.com: change file header line order]
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Board is a carrier board for Stamp9G20, with additional peripherals
for a building automation system
Signed-off-by: NPeter Gsellmann <pgsellmann@portner-elektronik.at>
[nicolas.ferre@atmel.com: remove machine_desc.io_pg_offst and .phys_io]
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: NSimon Guinot <sguinot@lacie.com>
Acked-by: NNicolas Pitre <nico@fluxnic.net>
Signed-off-by: NGuenter Roeck <guenter.roeck@ericsson.com>

Commit ab69bcd6 (arm: remove
machine_desc.io_pg_offst and .phys_io) could not update
the new boards in the omap tree. This causes the build of
omap2plus_defconfig to fail. Fix this.
Signed-off-by: NAnand Gadiyar <gadiyar@ti.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: Eric Miao <eric.miao at canonical.com>
[tony@atomide.com: updated description]
Signed-off-by: NTony Lindgren <tony@atomide.com>

On OMAP24xx, UART2 WKEN and WKST registers are in PM_WKEN2_CORE and
PM_WKST2_CORE respecitvely.  Fix the OMAP2 register init to use the
correct registers on OMAP24xx.
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

this patch gives the possibility to workaround bug ENGcm09152
on i.MX35 when the hardware workaround is also implemented on
the board.
It covers the workaround described on page 25 of the following Errata :
http://cache.freescale.com/files/dsp/doc/errata/IMX35CE.pdfSigned-off-by: NEric Bénard <eric@eukrea.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

AM35x has musb interface (version 1.8) and uses CPPI41 DMA engine.
It has USB phy built inside the IP itself.
Signed-off-by: NAjay Kumar Gupta <ajay.gupta@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Signed-off-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

This patch converts arm to use asm-generic/ioctls.h instead of its
own version.

The differences between the arch-specific version and the generic
version are as follows:

- ARM defines its own value for FIOQSIZE, asm-generic/ioctls.h keeps it
- The generic version adds support for termiox
Reviewed-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NJeff Mahoney <jeffm@suse.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

Signed-off-by: NMike Rapoport <mike@compulab.co.il>
CC: Olof Johansson <olof@lixom.net>
CC: Gary King <GKing@nvidia.com>
Signed-off-by: NColin Cross <ccross@android.com>

Change-Id: Ibd0bcd46895eb88952b9db29e1f68572d39aae01
Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Acked-by: NArnd Bergmann <arnd@arndb.de>
CC: Russell King <linux@arm.linux.org.uk>
CC: Gary King <GKing@nvidia.com>
Signed-off-by: NColin Cross <ccross@android.com>

Signed-off-by: NMike Rapoport <mike@compulab.co.il>
CC: Gary King <GKing@nvidia.com>
Signed-off-by: NColin Cross <ccross@android.com>

The APB DMA block handles DMA transfers to and from some peripherals
in the Tegra SOC.  It reads from sequential addresses on the memory
bus, and writes repeatedly to the same address on the APB bus.

Two transfer modes are supported, oneshot for transferring a known
size to or from a peripheral, and continuous for streaming data.
In continuous mode, a callback occurs when the buffer is half full
to allow the existing data to be handled and a new request queued.x

v2 changes:
	dma API no longer uses PTR_ERR
Signed-off-by: NErik Gilling <konkers@android.com>
Signed-off-by: NColin Cross <ccross@android.com>

Implement cpufreq support for the Tegra SOC.  DVFS is handled by the
core virtual cpu clock.  The frequencies of the two cores are tied
together, the highest frequency requested by either core determines
the actual frequency.
Signed-off-by: NColin Cross <ccross@android.com>

Renames clocks in the clock init table to match the datasheet names
Signed-off-by: NColin Cross <ccross@android.com>

- Add drivers to clock lookup table
- Add new pll_m entries
- Support I2C U16 divider
- Fix rate reporting on 32.768kHz clock
- Call propagate rate only if set_rate succeeds
- Add support for audio_sync clock
- Add 24MHz to PLLA frequency list
- Correct i2s1/2/spdifout mux
- Add suspend support
- Fix enable/disable parent clocks in set_parent
- Add max_rate parameter to all clocks
- DVFS support
- Add virtual cpu clock with dvfs
- Support clk_round_rate
- Fix requesting very high periph frequencies
- Add quirks for PLLU:
   PLLU is slightly different from the rest of the PLLs.  The
   lock enable bit is at bit 22 instead of 18 in the MISC
   register, and the post divider field is a single bit with
   reversed values from other PLLs.
- Simplify recalculating clock rates
- Fix UART divider flags
- Remove unused clock ops
Signed-off-by: NColin Cross <ccross@android.com>

The Tegra SOC contains fuses to identify the CPU type and
bin, and a unique id.  The CPU info is required to determine
the correct voltages for each cpu and core frequency.
Signed-off-by: NColin Cross <ccross@android.com>

Includes checkpatch fixes and TEGRA_NR_GPIOS changes from
Mike Rapoport <mike@compulab.co.il>
Signed-off-by: NColin Cross <ccross@android.com>

- the reset values for some pin groups in the tegra pin mux can result in
functional errors due to conflicting with actively-configured pin groups
muxing from the same controller. this change adds a known safe, non-
conflicting mux for every pin group, which can be used on platforms
where the pin group is not routed to any peripheral

- also add each pin group's I/O voltage rail, to enable platform code to
map from the pin groups used by each interface to the regulators used
for dynamic voltage control

- add routines to individually configure the tristate, pin mux and pull-
ups for a pingroup_config array, so that it is possible to program
individual values at run-time without modifying other values.
this allows driver power-management code to reprogram individual
interfaces into lower power states during idle / suspend, or to
reprogram the pin mux to support multiple physical busses per
internal controller (e.g., sharing a single I2C or SPI controller
across multiple pin groups)

- move chip-specific data like pingroups and drive-pingroups
out of the common code and into chip-specific code

- fix debug output for group with no pullups

- add a TEGRA_MUX_SAFE function.  Setting a pingroup to TEGRA_MUX_SAFE
will automatically select a mux setting that is guaranteed not to
conflict with any of the hardware blocks.
Signed-off-by: NGary King <gking@nvidia.com>

mirror IRQ enable and disable operations on the legacy PPI system
interrupt controller, since the legacy controller is responsible
for responding to wakeup interrupts when the CPU is in LP2 idle mode

save the irq controller state on suspend and restore on resume
Signed-off-by: NGary King <gking@nvidia.com>

The "legacy irq controller" duplicates the functionality of the GIC,
but remains powered during the cpu suspend and idle modes that power
down the CPU and the GIC.
Signed-off-by: NColin Cross <ccross@android.com>

Add missing io address map entries from datasheet.
Add the IRAM area to the statically mapped io regions.
Correct the onewire, USB, and statmon addresses
Signed-off-by: NColin Cross <ccross@android.com>

Some boards that were added after the mass io_pgoffst/io_physio
removal, and were not updated in the original patch.  Fixup here.

c.f. original io_pgoffst/io_physio removal
     commit 6451d778Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Since we're now using addruart to establish the debug mapping, we can
remove the io_pg_offst and phys_io members of struct machine_desc.

The various declarations were removed using the following script:

  grep -rl MACHINE_START arch/arm | xargs \
  sed -i '/MACHINE_START/,/MACHINE_END/ { /\.\(phys_io\|io_pg_offst\)/d }'

[ Initial patch was from Jeremy Kerr, example script from Russell King ]
Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Eric Miao <eric.miao at canonical.com>

Since we can get both physical and virtual addresses from the addruart
macro, we can use this to establish the debug mappings.

In the case of CONFIG_DEBUG_ICEDCC, we don't need any mappings, but
may still need to setup r7 correctly.

Incorporating ASM changes from Nicolas Pitre <npitre@fluxnic.net>.
Signed-off-by: NJeremy Kerr <jeremy.kerr@canonical.com>
Tested-by: NKevin Hilman <khilman@deeprootsystems.com>

Rather than checking the MMU status in every instance of addruart, do it
once in kernel/debug.S, and change the existing addruart macros to
return both physical and virtual addresses. The main debug code can then
select the appropriate address to use.

This will also allow us to retreive the address of a uart for the MMU
state that we're not current in.

Updated with fixes for OMAP from Jason Wang <jason77.wang@gmail.com>
and Tony Lindgren <tony@atomide.com>, and fix for versatile express from
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>.
Signed-off-by: NJeremy Kerr <jeremy.kerr@canonical.com>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NJason Wang <jason77.wang@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Tested-by: NKevin Hilman <khilman@deeprootsystems.com>

We have the same (empty) macro for all IDEDCC flavours, so consolidate
it to one.
Signed-off-by: NJeremy Kerr <jeremy.kerr@canonical.com>

As mentioned in the comment right at the top, the first four fields
are directly accessed by assembly code in head.S.  Move nr_irqs so the
comment is true again.
Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>

Pass the correct GPIO to gpio_free
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NEric Bénard <eric@eukrea.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

without this patch we get :
arch/arm/mach-imx/built-in.o: In function `eukrea_cpuimx27_init':
eukrea_mbimx27-baseboard.c:(.init.text+0x44c): undefined reference to `mxc_ulpi_access_ops'
Signed-off-by: NEric Bénard <eric@eukrea.com>
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>

this patch fix the following errors :
arch/arm/mach-mx3/mach-pcm037_eet.c:62: error: implicit declaration of function 'MXC_SPI_CS'
arch/arm/mach-mx3/mach-pcm037_eet.c:185: error: implicit declaration of function 'imx35_add_spi_imx0'

from the Kconfig pcm037 is i.MX31 based and not i.MX35 so replace
imx35_add_spi_imx0 by imx31_add_spi_imx0
Signed-off-by: NEric Bénard <eric@eukrea.com>
[ukl: remove unneeded #include <mach/spi.h>]
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>

This is only a partial revert of "ARM: mx3/mx31ads: fold board
header in its only user"
[commit ccfa7c26)]

As some of the the board defines are also used in the cs89x0
ethernet driver by the i.MX31 ADS.
Signed-off-by: NIan Lartey <ian@opensource.wolfsonmicro.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

add NAND, SDHC
Signed-off-by: NEric Bénard <eric@eukrea.com>

Signed-off-by: NEric Bénard <eric@eukrea.com>

this patch really configure the GPIO in GPIO mode.
Signed-off-by: NEric Bénard <eric@eukrea.com>

Tested on i.MX25 and i.MX35 and i.MX51
Signed-off-by: NEric Bénard <eric@eukrea.com>

the attached patch allows SD to work on i.MX51 with Wolfram's drivers
Tested on i.MX51.

Based on original patch from: Richard Zhu <r65037@freescale.com>
Signed-off-by: NEric Bénard <eric@eukrea.com>

Based on original patch from: Richard Zhu <r65037@freescale.com>
Signed-off-by: NEric Bénard <eric@eukrea.com>

Signed-off-by: NEric Bénard <eric@eukrea.com>