1. 13 6月, 2015 3 次提交
    • B
      Merge branches 'pci/aspm', 'pci/enumeration', 'pci/hotplug', 'pci/misc',... · 0ff9b9ba
      Bjorn Helgaas 提交于
      Merge branches 'pci/aspm', 'pci/enumeration', 'pci/hotplug', 'pci/misc', 'pci/msi', 'pci/resource' and 'pci/virtualization' into next
      
      * pci/aspm:
        PCI/ASPM: Simplify Clock Power Management setting
        PCI: Use dev->has_secondary_link to find downstream PCIe links
        PCI/ASPM: Use dev->has_secondary_link to find downstream links
        PCI: Add dev->has_secondary_link to track downstream PCIe links
        PCI/ASPM: Remove redundant PCIe port type checking
        PCI/ASPM: Drop __pci_disable_link_state() useless "force" parameter
      
      * pci/enumeration:
        PCI: Remove unused pci_scan_bus_parented()
        xen/pcifront: Don't use deprecated function pci_scan_bus_parented()
        PCI: designware: Use pci_scan_root_bus() for simplicity
        PCI: tegra: Remove tegra_pcie_scan_bus()
        PCI: mvebu: Remove mvebu_pcie_scan_bus()
      
      * pci/hotplug:
        PCI: pciehp: Wait for hotplug command completion where necessary
        PCI: Propagate the "ignore hotplug" setting to parent
        ACPI / hotplug / PCI: Check ignore_hotplug for all downstream devices
        PCI: pciehp: Drop pointless label from pciehp_probe()
        PCI: pciehp: Drop pointless ACPI-based "slot detection" check
      
      * pci/misc:
        PCI: Remove unused pci_dma_burst_advice()
        PCI: Remove unused pcibios_select_root() (again)
        PCI: Remove unnecessary #includes of <asm/pci.h>
        PCI: Include <linux/pci.h>, not <asm/pci.h>
      
      * pci/msi:
        PCI/MSI: Remove unused pci_msi_off()
        PCI/MSI: Drop pci_msi_off() calls from quirks
        ntb: Drop pci_msi_off() call during probe
        virtio_pci: drop pci_msi_off() call during probe
        PCI/MSI: Disable MSI at enumeration even if kernel doesn't support MSI
        PCI/MSI: Export pci_msi_set_enable(), pci_msix_clear_and_set_ctrl()
        PCI/MSI: Rename msi_set_enable(), msix_clear_and_set_ctrl()
      
      * pci/resource:
        PCI: Add pci_bus_addr_t
      
      * pci/virtualization:
        ACPI / PCI: Account for ARI in _PRT lookups
        PCI: Move pci_ari_enabled() to global header
        PCI: Add function 1 DMA alias quirk for Marvell 9120
        PCI: Add ACS quirks for Intel 9-series PCH root ports
      0ff9b9ba
    • Y
      PCI: Remove unused pci_scan_bus_parented() · c0300089
      Yijing Wang 提交于
      No one uses pci_scan_bus_parented() any more, remove it.
      Signed-off-by: NYijing Wang <wangyijing@huawei.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      c0300089
    • A
      xen/pcifront: Don't use deprecated function pci_scan_bus_parented() · 515d425b
      Arnd Bergmann 提交于
      Use pci_scan_root_bus() instead of deprecated function
      pci_scan_bus_parented().
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NYijing Wang <wangyijing@huawei.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      CC: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
      CC: xen-devel@lists.xenproject.org
      515d425b
  2. 11 6月, 2015 1 次提交
  3. 09 6月, 2015 1 次提交
    • A
      PCI: pciehp: Wait for hotplug command completion where necessary · a5dd4b4b
      Alex Williamson 提交于
      The commit referenced below deferred waiting for command completion until
      the start of the next command, allowing hardware to do the latching
      asynchronously.  Unfortunately, being ready to accept a new command is the
      only indication we have that the previous command is completed.  In cases
      where we need that state change to be enabled, we must still wait for
      completion.  For instance, pciehp_reset_slot() attempts to disable anything
      that might generate a surprise hotplug on slots that support presence
      detection.  If we don't wait for those settings to latch before the
      secondary bus reset, we negate any value in attempting to prevent the
      spurious hotplug.
      
      Create a base function with optional wait and helper functions so that
      pcie_write_cmd() turns back into the "safe" interface which waits before
      and after issuing a command and add pcie_write_cmd_nowait(), which
      eliminates the trailing wait for asynchronous completion.  The following
      functions are returned to their previous behavior:
      
        pciehp_power_on_slot
        pciehp_power_off_slot
        pcie_disable_notification
        pciehp_reset_slot
      
      The rationale is that pciehp_power_on_slot() enables the link and therefore
      relies on completion of power-on.  pciehp_power_off_slot() and
      pcie_disable_notification() need a wait because data structures may be
      freed after these calls and continued signaling from the device would be
      unexpected.  And, of course, pciehp_reset_slot() needs to wait for the
      scenario outlined above.
      
      Fixes: 3461a068 ("PCI: pciehp: Wait for hotplug command completion lazily")
      Signed-off-by: NAlex Williamson <alex.williamson@redhat.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      CC: stable@vger.kernel.org	# v3.17+
      a5dd4b4b
  4. 08 6月, 2015 4 次提交
  5. 31 5月, 2015 1 次提交
    • A
      ACPI / PCI: Account for ARI in _PRT lookups · 917bfd93
      Alex Williamson 提交于
      The PCIe specification, rev 3.0, section 2.2.8.1, contains the following
      implementation note:
      
        Virtual Wire Mapping for INTx Interrupts From ARI Devices
      
        The implied Device Number for an ARI Device is 0.  When ARI-aware
        software (including BIOS and operating system) enables ARI Forwarding in
        the Downstream Port immediately above an ARI Device in order to access
        its Extended Functions, software must comprehend that the Downstream Port
        will use Device Number 0 for the virtual wire mappings of INTx interrupts
        coming from all Functions of the ARI Device.  If non-ARI-aware software
        attempts to determine the virtual wire mappings for Extended Functions,
        it can come up with incorrect mappings by examining the traditional
        Device Number field and finding it to be non-0.
      
      We account for this in pci_swizzle_interrupt_pin(), but it looks like we
      miss it here, looking for a _PRT entry with a slot matching the ARI device
      slot number.  This can cause errors like:
      
        pcieport 0000:80:03.0: can't derive routing for PCI INT B
        sfc 0000:82:01.1: PCI INT B: no GSI
      
      pci_dev.irq is then invalid, resulting in errors for drivers that attempt
      to enable INTx on the device.  Fix by using slot 0 for ARI enabled devices.
      Signed-off-by: NAlex Williamson <alex.williamson@redhat.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: NDon Dutile <ddutile@redhat.com>
      Acked-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      917bfd93
  6. 30 5月, 2015 3 次提交
  7. 28 5月, 2015 2 次提交
  8. 27 5月, 2015 2 次提交
    • Y
      PCI: mvebu: Remove mvebu_pcie_scan_bus() · 2dead00b
      Yijing Wang 提交于
      After b97ea289 ("PCI: Assign resources before drivers claim devices
      (pci_scan_root_bus())"), pci_scan_root_bus() no longer adds the devices, so
      it is equivalent to mvebu_pcie_scan_bus().
      
      Remove mvebu_pcie_scan_bus() (the hw.scan method), so we use the generic
      pci_scan_root_bus() path.  We also need to use pci_common_init_dev()
      instead of pci_common_init() so we can supply the host bridge device
      pointer.
      
      [bhelgaas: changelog]
      Tested-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      Signed-off-by: NYijing Wang <wangyijing@huawei.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
      CC: Jason Cooper <jason@lakedaemon.net>
      2dead00b
    • Y
      PCI/ASPM: Use dev->has_secondary_link to find downstream links · c8fc9339
      Yijing Wang 提交于
      We allocate pcie_link_state for the component at the upstream end of a
      Link.  Previously we did this by allocating pcie_link_state for Root Ports
      and Downstream Ports.  This works fine for the typical topology:
      
        00:1c.0 Root Port       [bridge to bus 02]
        02:00.0 Upstream Port   [bridge to bus 03]
        03:00.0 Downstream Port [bridge to bus 04]
        04:00.0 Endpoint or Switch Port
      
      However, it is possible to have a Root Port connected to a Downstream Port
      instead of an Upstream Port, as in Robert White's ATCA system:
      
        00:1c.0 Root Port       [bridge to bus 02]
        02:00.0 Downstream Port [bridge to bus 03]
        03:01.0 Downstream Port [bridge to bus 04]
        04:00.0 Endpoint or Switch Port
      
      In this topology, we wrongly allocated pcie_link_state for the 02:00.0
      Downstream Port, which is actually the *downstream* end of a link.  This
      led to the following NULL pointer dereference when we tried to connect this
      link into the tree of links starting at the 00:1c.0 Root Port:
      
        BUG: unable to handle kernel NULL pointer dereference at 0000000000000088
        IP: [<ffffffff81550324>] pcie_aspm_init_link_state+0x744/0x850
        Hardware name: Kontron B3001/B3001, BIOS 4.6.3 08/07/2012
        Call Trace:
         [<ffffffff8153b865>] pci_scan_slot+0xd5/0x120
         [<ffffffff8153ca1d>] pci_scan_child_bus+0x2d/0xd0
         ...
      
      Instead of relying on the component type to identify the upstream end of a
      link, use the "dev->has_secondary_link" field.
      
      This means it's now possible for an Upstream Port to have a link on its
      secondary side, so alloc_pcie_link_state() needs to connect links
      originating from both Upstream and Downstream Ports into the tree.
      
      [bhelgaas: changelog, add comment]
      Link: https://bugzilla.kernel.org/show_bug.cgi?id=94361
      Link: http://lkml.kernel.org/r/54EB81B2.4050904@pobox.comReported-by: NRobert White <rwhite@pobox.com>
      Signed-off-by: NYijing Wang <wangyijing@huawei.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      c8fc9339
  9. 23 5月, 2015 3 次提交
  10. 22 5月, 2015 3 次提交
    • Y
      PCI: Add dev->has_secondary_link to track downstream PCIe links · d0751b98
      Yijing Wang 提交于
      A PCIe Port is an interface to a Link.  A Root Port is a PCI-PCI bridge in
      a Root Complex and has a Link on its secondary (downstream) side.  For
      other Ports, the Link may be on either the upstream (closer to the Root
      Complex) or downstream side of the Port.
      
      The usual topology has a Root Port connected to an Upstream Port.  We
      previously assumed this was the only possible topology, and that a
      Downstream Port's Link was always on its downstream side, like this:
      
                        +---------------------+
        +------+        |          Downstream |
        | Root |        | Upstream       Port +--Link--
        | Port +--Link--+ Port                |
        +------+        |          Downstream |
                        |                Port +--Link--
                        +---------------------+
      
      But systems do exist (see URL below) where the Root Port is connected to a
      Downstream Port.  In this case, a Downstream Port's Link may be on either
      the upstream or downstream side:
      
                        +---------------------+
        +------+        |            Upstream |
        | Root |        | Downstream     Port +--Link--
        | Port +--Link--+ Port                |
        +------+        |          Downstream |
                        |                Port +--Link--
                        +---------------------+
      
      We can't use the Port type to determine which side the Link is on, so add a
      bit in struct pci_dev to keep track.
      
      A Root Port's Link is always on the Port's secondary side.  A component
      (Endpoint or Port) on the other end of the Link obviously has the Link on
      its upstream side.  If that component is a Port, it is part of a Switch or
      a Bridge.  A Bridge has a PCI or PCI-X bus on its secondary side, not a
      Link.  The internal bus of a Switch connects the Port to another Port whose
      Link is on the downstream side.
      
      [bhelgaas: changelog, comment, cache "type", use if/else]
      Link: http://lkml.kernel.org/r/54EB81B2.4050904@pobox.com
      Link: https://bugzilla.kernel.org/show_bug.cgi?id=94361Suggested-by: NBjorn Helgaas <bhelgaas@google.com>
      Signed-off-by: NYijing Wang <wangyijing@huawei.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      d0751b98
    • S
      PCI: Add function 1 DMA alias quirk for Marvell 9120 · 247de694
      Sakari Ailus 提交于
      Marvell 9120 SATA controller has the same issue as a number of others, so
      use the same quirk for this one.  The other quirks were added by
      cc346a47 ("PCI: Add function 1 DMA alias quirk for Marvell devices").
      Signed-off-by: NSakari Ailus <sakari.ailus@linux.intel.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Acked-by: NAlex Williamson <alex.williamson@redhat.com>
      247de694
    • R
      PCI: pciehp: Drop pointless ACPI-based "slot detection" check · e705c295
      Rafael J. Wysocki 提交于
      Jarod Wilson reports that ExpressCard hotplug doesn't work on HP ZBook G2.
      The problem turns out to be the ACPI-based "slot detection" code called
      from pciehp_probe() which uses questionable heuristics based on what ACPI
      objects are present for the PCIe port device to figure out whether to
      register a hotplug slot for that port.
      
      That code is used if there is at least one PCIe port having an ACPI device
      configuration object related to hotplug (such as _EJ0 or _RMV), and the
      Thunderbolt port on the ZBook has _RMV.  Of course, Thunderbolt and PCIe
      native hotplug need not be mutually exclusive (as they aren't on the
      ZBook), so that rule is simply incorrect.
      
      Moreover, the ACPI-based "slot detection" check does not add any value if
      pciehp_probe() is called at all and the service type of the device object
      it has been called for is PCIE_PORT_SERVICE_HP, because PCIe hotplug
      services are only registered if the _OSC handshake in acpi_pci_root_add()
      allows the kernel to control the PCIe native hotplug feature.  No more
      checks need to be carried out to decide whether or not to register a native
      PCIe hotlug slot in that case.
      
      For the above reasons, make pciehp_probe() check if it has been called for
      the right service type and drop the pointless ACPI-based "slot detection"
      check from it.  Also remove the entire code whose only user is that check
      (the entire pciehp_acpi.c file goes away as a result) and drop function
      headers related to it from the internal pciehp header file.
      
      Link: http://lkml.kernel.org/r/1431632038-39917-1-git-send-email-jarod@redhat.com
      Link: https://bugzilla.kernel.org/show_bug.cgi?id=98581Reported-by: NJarod Wilson <jarod@redhat.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Reviewed-by: NJarod Wilson <jarod@redhat.com>
      Tested-by: NJarod Wilson <jarod@redhat.com>
      e705c295
  11. 21 5月, 2015 2 次提交
  12. 16 5月, 2015 1 次提交
  13. 07 5月, 2015 7 次提交
  14. 04 5月, 2015 7 次提交