- 13 6月, 2015 3 次提交
-
-
由 Bjorn Helgaas 提交于
Merge branches 'pci/aspm', 'pci/enumeration', 'pci/hotplug', 'pci/misc', 'pci/msi', 'pci/resource' and 'pci/virtualization' into next * pci/aspm: PCI/ASPM: Simplify Clock Power Management setting PCI: Use dev->has_secondary_link to find downstream PCIe links PCI/ASPM: Use dev->has_secondary_link to find downstream links PCI: Add dev->has_secondary_link to track downstream PCIe links PCI/ASPM: Remove redundant PCIe port type checking PCI/ASPM: Drop __pci_disable_link_state() useless "force" parameter * pci/enumeration: PCI: Remove unused pci_scan_bus_parented() xen/pcifront: Don't use deprecated function pci_scan_bus_parented() PCI: designware: Use pci_scan_root_bus() for simplicity PCI: tegra: Remove tegra_pcie_scan_bus() PCI: mvebu: Remove mvebu_pcie_scan_bus() * pci/hotplug: PCI: pciehp: Wait for hotplug command completion where necessary PCI: Propagate the "ignore hotplug" setting to parent ACPI / hotplug / PCI: Check ignore_hotplug for all downstream devices PCI: pciehp: Drop pointless label from pciehp_probe() PCI: pciehp: Drop pointless ACPI-based "slot detection" check * pci/misc: PCI: Remove unused pci_dma_burst_advice() PCI: Remove unused pcibios_select_root() (again) PCI: Remove unnecessary #includes of <asm/pci.h> PCI: Include <linux/pci.h>, not <asm/pci.h> * pci/msi: PCI/MSI: Remove unused pci_msi_off() PCI/MSI: Drop pci_msi_off() calls from quirks ntb: Drop pci_msi_off() call during probe virtio_pci: drop pci_msi_off() call during probe PCI/MSI: Disable MSI at enumeration even if kernel doesn't support MSI PCI/MSI: Export pci_msi_set_enable(), pci_msix_clear_and_set_ctrl() PCI/MSI: Rename msi_set_enable(), msix_clear_and_set_ctrl() * pci/resource: PCI: Add pci_bus_addr_t * pci/virtualization: ACPI / PCI: Account for ARI in _PRT lookups PCI: Move pci_ari_enabled() to global header PCI: Add function 1 DMA alias quirk for Marvell 9120 PCI: Add ACS quirks for Intel 9-series PCH root ports
-
由 Yijing Wang 提交于
No one uses pci_scan_bus_parented() any more, remove it. Signed-off-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
由 Arnd Bergmann 提交于
Use pci_scan_root_bus() instead of deprecated function pci_scan_bus_parented(). Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> CC: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> CC: xen-devel@lists.xenproject.org
-
- 11 6月, 2015 1 次提交
-
-
由 Bjorn Helgaas 提交于
Update the Link Control Enable Clock Power Management bit the same way we update the ASPM Control bits, with a single call of pcie_capability_clear_and_set_word(). No functional change; this just makes both paths use the same style. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
- 09 6月, 2015 1 次提交
-
-
由 Alex Williamson 提交于
The commit referenced below deferred waiting for command completion until the start of the next command, allowing hardware to do the latching asynchronously. Unfortunately, being ready to accept a new command is the only indication we have that the previous command is completed. In cases where we need that state change to be enabled, we must still wait for completion. For instance, pciehp_reset_slot() attempts to disable anything that might generate a surprise hotplug on slots that support presence detection. If we don't wait for those settings to latch before the secondary bus reset, we negate any value in attempting to prevent the spurious hotplug. Create a base function with optional wait and helper functions so that pcie_write_cmd() turns back into the "safe" interface which waits before and after issuing a command and add pcie_write_cmd_nowait(), which eliminates the trailing wait for asynchronous completion. The following functions are returned to their previous behavior: pciehp_power_on_slot pciehp_power_off_slot pcie_disable_notification pciehp_reset_slot The rationale is that pciehp_power_on_slot() enables the link and therefore relies on completion of power-on. pciehp_power_off_slot() and pcie_disable_notification() need a wait because data structures may be freed after these calls and continued signaling from the device would be unexpected. And, of course, pciehp_reset_slot() needs to wait for the scenario outlined above. Fixes: 3461a068 ("PCI: pciehp: Wait for hotplug command completion lazily") Signed-off-by: NAlex Williamson <alex.williamson@redhat.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.17+
-
- 08 6月, 2015 4 次提交
-
-
由 Bjorn Helgaas 提交于
pci_dma_burst_advice() was added by e24c2d96 ("[PATCH] PCI: DMA bursting advice") but apparently never used. Remove it. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <monstr@monstr.eu> # microblaze CC: David S. Miller <davem@davemloft.net>
-
由 Bjorn Helgaas 提交于
a6c14096 ("Delete pcibios_select_root") removed pcibios_select_root(). But a7db5040 ("PCI: remove pcibios_scan_all_fns()") added a few copies back, probably with some incorrect merge conflict resolutions. Remove the still-unused pcibios_select_root() definitions. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
由 Bjorn Helgaas 提交于
In include/linux/pci.h, we already #include <asm/pci.h>, so we don't need to include <asm/pci.h> directly. Remove the unnecessary includes. All the files here already include <linux/pci.h>. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> # sh Acked-by: NRalf Baechle <ralf@linux-mips.org>
-
由 Bjorn Helgaas 提交于
We already include <asm/pci.h> from <linux/pci.h>, so just include <linux/pci.h> directly. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> CC: linuxppc-dev@lists.ozlabs.org CC: linux-s390@vger.kernel.org
-
- 31 5月, 2015 1 次提交
-
-
由 Alex Williamson 提交于
The PCIe specification, rev 3.0, section 2.2.8.1, contains the following implementation note: Virtual Wire Mapping for INTx Interrupts From ARI Devices The implied Device Number for an ARI Device is 0. When ARI-aware software (including BIOS and operating system) enables ARI Forwarding in the Downstream Port immediately above an ARI Device in order to access its Extended Functions, software must comprehend that the Downstream Port will use Device Number 0 for the virtual wire mappings of INTx interrupts coming from all Functions of the ARI Device. If non-ARI-aware software attempts to determine the virtual wire mappings for Extended Functions, it can come up with incorrect mappings by examining the traditional Device Number field and finding it to be non-0. We account for this in pci_swizzle_interrupt_pin(), but it looks like we miss it here, looking for a _PRT entry with a slot matching the ARI device slot number. This can cause errors like: pcieport 0000:80:03.0: can't derive routing for PCI INT B sfc 0000:82:01.1: PCI INT B: no GSI pci_dev.irq is then invalid, resulting in errors for drivers that attempt to enable INTx on the device. Fix by using slot 0 for ARI enabled devices. Signed-off-by: NAlex Williamson <alex.williamson@redhat.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NDon Dutile <ddutile@redhat.com> Acked-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
-
- 30 5月, 2015 3 次提交
-
-
由 Yinghai Lu 提交于
David Ahern reported that d63e2e1f ("sparc/PCI: Clip bridge windows to fit in upstream windows") fails to boot on sparc/T5-8: pci 0000:06:00.0: reg 0x184: can't handle BAR above 4GB (bus address 0x110204000) The problem is that sparc64 assumed that dma_addr_t only needed to hold DMA addresses, i.e., bus addresses returned via the DMA API (dma_map_single(), etc.), while the PCI core assumed dma_addr_t could hold *any* bus address, including raw BAR values. On sparc64, all DMA addresses fit in 32 bits, so dma_addr_t is a 32-bit type. However, BAR values can be 64 bits wide, so they don't fit in a dma_addr_t. d63e2e1f added new checking that tripped over this mismatch. Add pci_bus_addr_t, which is wide enough to hold any PCI bus address, including both raw BAR values and DMA addresses. This will be 64 bits on 64-bit platforms and on platforms with a 64-bit dma_addr_t. Then dma_addr_t only needs to be wide enough to hold addresses from the DMA API. [bhelgaas: changelog, bugzilla, Kconfig to ensure pci_bus_addr_t is at least as wide as dma_addr_t, documentation] Fixes: d63e2e1f ("sparc/PCI: Clip bridge windows to fit in upstream windows") Fixes: 23b13bc7 ("PCI: Fail safely if we can't handle BARs larger than 4GB") Link: http://lkml.kernel.org/r/CAE9FiQU1gJY1LYrxs+ma5LCTEEe4xmtjRG0aXJ9K_Tsu+m9Wuw@mail.gmail.com Link: http://lkml.kernel.org/r/1427857069-6789-1-git-send-email-yinghai@kernel.org Link: https://bugzilla.kernel.org/show_bug.cgi?id=96231Reported-by: NDavid Ahern <david.ahern@oracle.com> Tested-by: NDavid Ahern <david.ahern@oracle.com> Signed-off-by: NYinghai Lu <yinghai@kernel.org> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NDavid S. Miller <davem@davemloft.net> CC: stable@vger.kernel.org # v3.19+
-
由 Alex Williamson 提交于
pci_ari_enabled() is useful outside of drivers/pci, particularly for deriving INTx routing via ACPI _PRT, so move it to the global header. Also convert to bool return. Signed-off-by: NAlex Williamson <alex.williamson@redhat.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NDon Dutile <ddutile@redhat.com> Acked-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
-
由 Yijing Wang 提交于
Previously we assumed that PCIe Root Ports and Downstream Ports had Links on their secondary side. That is true in most systems, but it is possible to connect a switch with either an Upstream or a Downstream Port leading downstream. Instead of relying on the component type to identify devices that have links leading downstream, use the "dev->has_secondary_link" field. [bhelgaas: changelog] Signed-off-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
- 28 5月, 2015 2 次提交
-
-
由 Yijing Wang 提交于
After b97ea289 ("PCI: Assign resources before drivers claim devices (pci_scan_root_bus())"), pci_scan_root_bus() no longer adds the devices, so it is equivalent to: pci_create_root_bus() pci_scan_child_bus() Use pci_scan_root_bus() to simplify the code. [bhelgaas: changelog] Signed-off-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NLucas Stach <l.stach@pengutronix.de> Acked-by: NJingoo Han <jingoohan1@gmail.com> CC: Mohit Kumar <mohit.kumar@st.com>
-
由 Yijing Wang 提交于
After b97ea289 ("PCI: Assign resources before drivers claim devices (pci_scan_root_bus())"), pci_scan_root_bus() no longer adds the devices, so it is equivalent to tegra_pcie_scan_bus(). Remove tegra_pcie_scan_bus() (the hw.scan method), so we use the generic pci_scan_root_bus() path. [bhelgaas: changelog] Tested-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NThierry Reding <treding@nvidia.com>
-
- 27 5月, 2015 2 次提交
-
-
由 Yijing Wang 提交于
After b97ea289 ("PCI: Assign resources before drivers claim devices (pci_scan_root_bus())"), pci_scan_root_bus() no longer adds the devices, so it is equivalent to mvebu_pcie_scan_bus(). Remove mvebu_pcie_scan_bus() (the hw.scan method), so we use the generic pci_scan_root_bus() path. We also need to use pci_common_init_dev() instead of pci_common_init() so we can supply the host bridge device pointer. [bhelgaas: changelog] Tested-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NGregory CLEMENT <gregory.clement@free-electrons.com> CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> CC: Jason Cooper <jason@lakedaemon.net>
-
由 Yijing Wang 提交于
We allocate pcie_link_state for the component at the upstream end of a Link. Previously we did this by allocating pcie_link_state for Root Ports and Downstream Ports. This works fine for the typical topology: 00:1c.0 Root Port [bridge to bus 02] 02:00.0 Upstream Port [bridge to bus 03] 03:00.0 Downstream Port [bridge to bus 04] 04:00.0 Endpoint or Switch Port However, it is possible to have a Root Port connected to a Downstream Port instead of an Upstream Port, as in Robert White's ATCA system: 00:1c.0 Root Port [bridge to bus 02] 02:00.0 Downstream Port [bridge to bus 03] 03:01.0 Downstream Port [bridge to bus 04] 04:00.0 Endpoint or Switch Port In this topology, we wrongly allocated pcie_link_state for the 02:00.0 Downstream Port, which is actually the *downstream* end of a link. This led to the following NULL pointer dereference when we tried to connect this link into the tree of links starting at the 00:1c.0 Root Port: BUG: unable to handle kernel NULL pointer dereference at 0000000000000088 IP: [<ffffffff81550324>] pcie_aspm_init_link_state+0x744/0x850 Hardware name: Kontron B3001/B3001, BIOS 4.6.3 08/07/2012 Call Trace: [<ffffffff8153b865>] pci_scan_slot+0xd5/0x120 [<ffffffff8153ca1d>] pci_scan_child_bus+0x2d/0xd0 ... Instead of relying on the component type to identify the upstream end of a link, use the "dev->has_secondary_link" field. This means it's now possible for an Upstream Port to have a link on its secondary side, so alloc_pcie_link_state() needs to connect links originating from both Upstream and Downstream Ports into the tree. [bhelgaas: changelog, add comment] Link: https://bugzilla.kernel.org/show_bug.cgi?id=94361 Link: http://lkml.kernel.org/r/54EB81B2.4050904@pobox.comReported-by: NRobert White <rwhite@pobox.com> Signed-off-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
- 23 5月, 2015 3 次提交
-
-
由 Rafael J. Wysocki 提交于
Refine the mechanism introduced by commit f244d8b6 ("ACPIPHP / radeon / nouveau: Fix VGA switcheroo problem related to hotplug") to propagate the ignore_hotplug setting of the device to its parent bridge in case hotplug notifications related to the graphics adapter switching are given for the bridge rather than for the device itself (they need to be ignored in both cases). Link: https://bugzilla.kernel.org/show_bug.cgi?id=61891 Link: https://bugs.freedesktop.org/show_bug.cgi?id=88927 Fixes: b440bde7 ("PCI: Add pci_ignore_hotplug() to ignore hotplug events for a device") Reported-and-tested-by: Ntiagdtd-lava <tiagdtd-lava@yahoo.de> Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.17+
-
由 Rafael J. Wysocki 提交于
If the ignore_hotplug flag is set for a PCI device without an ACPI companion and a bus check notification is received for an ancestor bridge that is not the device's parent, ACPIPHP will ignore that flag. Namely, in that case acpiphp_check_bridge() is called for the target bridge and if all of the devices immediately below the bridge are still present, trim_stale_devices() will be called for each of them. That function recursively walks the hierarchy downwards and removes device objects corresponding to devices that don't appear to be present any more. Unfortunately, it only checks ignore_hotplug for devices having ACPI companions, so it will remove the others (if they don't respond) regardless of the ignore_hotplug value. Fix the problem by making trim_stale_devices() take ignore_hotplug into consideration regardless of whether or not an ACPI companion is present for the device it has been called for. [bhelgaas: This may fix bug 61891, depending on whether the bridge above a device is removed along with the device] Link: https://bugzilla.kernel.org/show_bug.cgi?id=61891Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
由 Rafael J. Wysocki 提交于
The err_out_none label in pciehp_probe() only leads to a return statement, so use return statements instead of jumps to it and drop it. Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
- 22 5月, 2015 3 次提交
-
-
由 Yijing Wang 提交于
A PCIe Port is an interface to a Link. A Root Port is a PCI-PCI bridge in a Root Complex and has a Link on its secondary (downstream) side. For other Ports, the Link may be on either the upstream (closer to the Root Complex) or downstream side of the Port. The usual topology has a Root Port connected to an Upstream Port. We previously assumed this was the only possible topology, and that a Downstream Port's Link was always on its downstream side, like this: +---------------------+ +------+ | Downstream | | Root | | Upstream Port +--Link-- | Port +--Link--+ Port | +------+ | Downstream | | Port +--Link-- +---------------------+ But systems do exist (see URL below) where the Root Port is connected to a Downstream Port. In this case, a Downstream Port's Link may be on either the upstream or downstream side: +---------------------+ +------+ | Upstream | | Root | | Downstream Port +--Link-- | Port +--Link--+ Port | +------+ | Downstream | | Port +--Link-- +---------------------+ We can't use the Port type to determine which side the Link is on, so add a bit in struct pci_dev to keep track. A Root Port's Link is always on the Port's secondary side. A component (Endpoint or Port) on the other end of the Link obviously has the Link on its upstream side. If that component is a Port, it is part of a Switch or a Bridge. A Bridge has a PCI or PCI-X bus on its secondary side, not a Link. The internal bus of a Switch connects the Port to another Port whose Link is on the downstream side. [bhelgaas: changelog, comment, cache "type", use if/else] Link: http://lkml.kernel.org/r/54EB81B2.4050904@pobox.com Link: https://bugzilla.kernel.org/show_bug.cgi?id=94361Suggested-by: NBjorn Helgaas <bhelgaas@google.com> Signed-off-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
由 Sakari Ailus 提交于
Marvell 9120 SATA controller has the same issue as a number of others, so use the same quirk for this one. The other quirks were added by cc346a47 ("PCI: Add function 1 DMA alias quirk for Marvell devices"). Signed-off-by: NSakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NAlex Williamson <alex.williamson@redhat.com>
-
由 Rafael J. Wysocki 提交于
Jarod Wilson reports that ExpressCard hotplug doesn't work on HP ZBook G2. The problem turns out to be the ACPI-based "slot detection" code called from pciehp_probe() which uses questionable heuristics based on what ACPI objects are present for the PCIe port device to figure out whether to register a hotplug slot for that port. That code is used if there is at least one PCIe port having an ACPI device configuration object related to hotplug (such as _EJ0 or _RMV), and the Thunderbolt port on the ZBook has _RMV. Of course, Thunderbolt and PCIe native hotplug need not be mutually exclusive (as they aren't on the ZBook), so that rule is simply incorrect. Moreover, the ACPI-based "slot detection" check does not add any value if pciehp_probe() is called at all and the service type of the device object it has been called for is PCIE_PORT_SERVICE_HP, because PCIe hotplug services are only registered if the _OSC handshake in acpi_pci_root_add() allows the kernel to control the PCIe native hotplug feature. No more checks need to be carried out to decide whether or not to register a native PCIe hotlug slot in that case. For the above reasons, make pciehp_probe() check if it has been called for the right service type and drop the pointless ACPI-based "slot detection" check from it. Also remove the entire code whose only user is that check (the entire pciehp_acpi.c file goes away as a result) and drop function headers related to it from the internal pciehp header file. Link: http://lkml.kernel.org/r/1431632038-39917-1-git-send-email-jarod@redhat.com Link: https://bugzilla.kernel.org/show_bug.cgi?id=98581Reported-by: NJarod Wilson <jarod@redhat.com> Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NJarod Wilson <jarod@redhat.com> Tested-by: NJarod Wilson <jarod@redhat.com>
-
- 21 5月, 2015 2 次提交
-
-
由 Yijing Wang 提交于
We decide in alloc_pcie_link_state() whether to allocate a pcie_link_state for a device. After that, it's sufficient to check pdev->link_state. We don't need to check the PCIe port type again. Remove the redundant PCIe port type checking. [bhelgaas: changelog] Signed-off-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
由 Bjorn Helgaas 提交于
After 387d3757 ("PCI: Don't clear ASPM bits when the FADT declares it's unsupported"), the "force" parameter to __pci_disable_link_state() is always "false". Remove the "force" parameter and assume it's always false. Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
- 16 5月, 2015 1 次提交
-
-
由 Alex Williamson 提交于
Intel confirms that 9-series chipset root ports provide ACS-equivalent isolation when configured via the existing Intel PCH ACS quirk setup. Signed-off-by: NAlex Williamson <alex.williamson@redhat.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NDon Dugger <donald.d.dugger@intel.com>
-
- 07 5月, 2015 7 次提交
-
-
由 Bjorn Helgaas 提交于
pci_msi_off() is unused, so remove it. Removes the exported symbol pci_msi_off(). Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
由 Michael S. Tsirkin 提交于
The PCI core now disables MSI and MSI-X for all devices during enumeration regardless of CONFIG_PCI_MSI. Remove device-specific code to disable MSI/MSI-X. Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
由 Michael S. Tsirkin 提交于
The PCI core now disables MSI and MSI-X for all devices during enumeration regardless of CONFIG_PCI_MSI. Remove device-specific code to disable MSI/MSI-X. Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
由 Michael S. Tsirkin 提交于
The PCI core now disables MSI and MSI-X for all devices during enumeration regardless of CONFIG_PCI_MSI. Remove device-specific code to disable MSI/MSI-X. Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
由 Michael S. Tsirkin 提交于
If we enable MSI, then kexec a new kernel, the new kernel may receive MSIs it is not prepared for. Commit d5dea7d9 ("PCI: msi: Disable msi interrupts when we initialize a pci device") prevents this, but only if the new kernel is built with CONFIG_PCI_MSI=y. Move the "disable MSI" functionality from drivers/pci/msi.c to a new pci_msi_setup_pci_dev() in drivers/pci/probe.c so we can disable MSIs when we enumerate devices even if the kernel doesn't include full MSI support. [bhelgaas: changelog, disable MSIs in pci_setup_device(), put pci_msi_setup_pci_dev() at its final destination] Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
-
由 Michael S. Tsirkin 提交于
Move pci_msi_set_enable() and pci_msix_clear_and_set_ctrl() to drivers/pci/pci.h so they're available even when MSI isn't configured into the kernel. No functional change. [bhelgaas: changelog, split into separate patch] Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NFam Zheng <famz@redhat.com>
-
由 Michael S. Tsirkin 提交于
Rename msi_set_enable() to pci_msi_set_enable() and msix_clear_and_set_ctrl() to pci_msix_clear_and_set_ctrl(). No functional change. [bhelgaas: changelog, split into separate patch] Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NFam Zheng <famz@redhat.com>
-
- 04 5月, 2015 7 次提交
-
-
由 Linus Torvalds 提交于
-
git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4由 Linus Torvalds 提交于
Pull ext4 fixes from Ted Ts'o: "Some miscellaneous bug fixes and some final on-disk and ABI changes for ext4 encryption which provide better security and performance" * tag 'for_linus_stable' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4: ext4: fix growing of tiny filesystems ext4: move check under lock scope to close a race. ext4: fix data corruption caused by unwritten and delayed extents ext4 crypto: remove duplicated encryption mode definitions ext4 crypto: do not select from EXT4_FS_ENCRYPTION ext4 crypto: add padding to filenames before encrypting ext4 crypto: simplify and speed up filename encryption
-
git://people.freedesktop.org/~airlied/linux由 Linus Torvalds 提交于
Pull drm fixes from Dave Airlie: "One intel fix, one rockchip fix, and a bunch of radeon fixes for some regressions from audio rework and vm stability" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/i915/chv: Implement WaDisableShadowRegForCpd drm/radeon: fix userptr return value checking (v2) drm/radeon: check new address before removing old one drm/radeon: reset BOs address after clearing it. drm/radeon: fix lockup when BOs aren't part of the VM on release drm/radeon: add SI DPM quirk for Sapphire R9 270 Dual-X 2G GDDR5 drm/radeon: adjust pll when audio is not enabled drm/radeon: only enable audio streams if the monitor supports it drm/radeon: only mark audio as connected if the monitor supports it (v3) drm/radeon/audio: don't enable packets until the end drm/radeon: drop dce6_dp_enable drm/radeon: fix ordering of AVI packet setup drm/radeon: Use drm_calloc_ab for CS relocs drm/rockchip: fix error check when getting irq MAINTAINERS: add entry for Rockchip drm drivers
-
git://anongit.freedesktop.org/drm-intel由 Dave Airlie 提交于
Just a single intel fix * tag 'drm-intel-fixes-2015-04-30' of git://anongit.freedesktop.org/drm-intel: drm/i915/chv: Implement WaDisableShadowRegForCpd
-
https://github.com/markyzq/kernel-drm-rockchip由 Dave Airlie 提交于
one fix and maintainers update * 'drm-next0420' of https://github.com/markyzq/kernel-drm-rockchip: drm/rockchip: fix error check when getting irq MAINTAINERS: add entry for Rockchip drm drivers
-
git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi由 Linus Torvalds 提交于
Pull SCSI fixes from James Bottomley: "This is three logical fixes (as 5 patches). The 3ware class of drivers were causing an oops with multiqueue by tearing down the command mappings after completing the command (where the variables in the command used to tear down the mapping were no-longer valid). There's also a fix for the qnap iscsi target which was choking on us sending it commands that were too long and a fix for the reworked aha1542 allocating GFP_KERNEL under a lock" * tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: 3w-9xxx: fix command completion race 3w-xxxx: fix command completion race 3w-sas: fix command completion race aha1542: Allocate memory before taking a lock SCSI: add 1024 max sectors black list flag
-
git://git.infradead.org/users/vkoul/slave-dma由 Linus Torvalds 提交于
Pull slave dmaengine fixes from Vinod Koul: "Here are the fixes in dmaengine subsystem for rc2: - privatecnt fix for slave dma request API by Christopher - warn fix for PM ifdef in usb-dmac by Geert - fix hardware dependency for xgene by Jean" * 'next' of git://git.infradead.org/users/vkoul/slave-dma: dmaengine: increment privatecnt when using dma_get_any_slave_channel dmaengine: xgene: Set hardware dependency dmaengine: usb-dmac: Protect PM-only functions to kill warning
-