- 17 12月, 2010 2 次提交
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由 Mario Kleiner 提交于
v2: Change IS_IRONLAKE to IS_GEN5 to adapt to 2.6.37 This patch adds new functions for use by the drm core: .get_vblank_timestamp() provides a precise timestamp for the end of the most recent (or current) vblank interval of a given crtc, as needed for the DRI2 implementation of the OML_sync_control extension. It is a thin wrapper around the drm function drm_calc_vbltimestamp_from_scanoutpos() which does almost all the work. .get_scanout_position() provides the current horizontal and vertical video scanout position and "in vblank" status of a given crtc, as needed by the drm for use by drm_calc_vbltimestamp_from_scanoutpos(). The patch modifies the pageflip completion routine to use these precise vblank timestamps as the timestamps for pageflip completion events. This code has been only tested on a HP-Mini Netbook with Atom processor and Intel 945GME gpu. The codepath for (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) gpu's has not been tested so far due to lack of hardware. Signed-off-by: NMario Kleiner <mario.kleiner@tuebingen.mpg.de> Acked-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
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- 16 12月, 2010 6 次提交
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由 Alex Deucher 提交于
Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Dave Airlie 提交于
* 'nouveau/drm-nouveau-next' of ../drm-nouveau-next: (93 commits) drm/nv50: fix a couple of vm init issues drm/nv04-nv40: Fix up PCI(E) GART DMA object bus address calculation. drm/nouveau: kick vram functions out into an "engine" drm/nouveau: allow gpuobj vinst to be a virtual address when necessary drm/nv50: tidy up PCIEGART implementation drm/nv50: enable non-contig vram allocations where requested drm/nv50: enable 4KiB pages for small vram allocations drm/nv50: implement global channel address space on new VM code drm/nv50: implement BAR1/BAR3 management on top of new VM code drm/nv50: import new vm code drm/nv50: implement custom vram mm drm/nouveau: Avoid potential race between nouveau_fence_update() and context takedown. drm/nouveau: fix use of drm_mm_node in semaphore object drm/nouveau: wrap calls to ttm_bo_validate() drm/nouveau: no need to zero dma objects, we fill them completely anyway drm/nouveau: introduce a util function to wait on reg != val drm/nouveau: implicitly insert non-DMA objects into RAMHT drm/nouveau: make fifo.create_context() responsible for mapping control regs drm/nouveau: Spin for a bit in nouveau_fence_wait() before yielding the CPU. drm/nouveau: Use WC memory on the AGP GART. ...
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由 Ben Skeggs 提交于
Drivers using their own implementation of io_mem_reserve/io_mem_free are likely to store the tracking information for the map in mem.mm_node, so it can't be freed while still mapped. Signed-off-by: Ben Skeggs<bskeggs@redhat.com> Reviewed-by: NThomas Hellstrom <thellstrom@vmware.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Dave Airlie 提交于
this adds a bo create, and fence seq tracking tracepoints. This is just an initial set to play around with, we should investigate what others we need would be useful. Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Francisco Jerez 提交于
Fixes overwriting the first page table entry when testing that the PRAMIN BAR can be correctly read/written, and adds an additional bar flush after poking the BAR3 control regs. Signed-off-by: NFrancisco Jerez <currojerez@riseup.net> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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- 15 12月, 2010 5 次提交
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由 Yuanhan Liu 提交于
Add frame buffer compression on Sandybridge. The method is similar to Ironlake, except that two new registers of type GTTMMADR must be written with the right fence info. Signed-off-by: NYuanhan Liu <yuanhan.liu@linux.intel.com> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Yuanhan Liu 提交于
Add the support of memory self-refresh on Sandybridge, which is now support 3 levels of watermarks and the source of the latency values for watermarks has changed. On Sandybridge, the LP0 WM value is not hardcoded any more. All the latency value is now should be extracted from MCHBAR SSKPD register. And the MCHBAR base address is changed, too. For the WM values, if any calculated watermark values is larger than the maximum value that can be programmed into the associated watermark register, that watermark must be disabled. Signed-off-by: NYuanhan Liu <yuanhan.liu@linux.intel.com> [ickle: remove duplicate compute routines and fixup for checkpatch] Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Be paranoid and ensure that the vblank has passed and the scanout has switched to the new fb, before unpinning the old one and possibly tearing down its PTEs. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Restore PIPE_CONTROL once again just for Ironlake, as it appears that MI_USER_INTERRUPT does not have the same coherency guarantees, that is on Ironlake the interrupt following a GPU write is not guaranteed to arrive after the write is coherent from the CPU, as it does on the other generations. Reported-by: NZhenyu Wang <zhenyuw@linux.intel.com> Reported-by: NShuang He <shuang.he@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32402Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
As we already know the limits for the hardware clock, pass it down rather than recomputing them for each match. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 14 12月, 2010 4 次提交
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由 Chris Wilson 提交于
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32288Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
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由 Chris Wilson 提交于
In order to enforce the correct memory barriers for irq get/put, we need to perform the actual counting using atomic operations. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
This fixes regression from a6963596, that missed to set cached memory type in GTT entry. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 10 12月, 2010 10 次提交
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由 Chris Wilson 提交于
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由 Chris Wilson 提交于
BIOSes. Can't live without them (apparently), definitely can't live with them. Reported-by: NBen Gamari <bgamari@gmail.com> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=24312Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Once we have read the value out of the GT power well, we need to remove the FORCE WAKE bit to allow the system to auto-power down. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Required for my pineview system to not barf after resuming. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
As suggested by Daniel Vetter, this is a safeguard should any of the registers cause reference to PTE entries. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
So we can remove the repeated initialisation. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
As we provide a list of all objects that will be accessed from the batchbuffer, we can build a lut of the handles associated with those objects for this invocation and use that to avoid the overhead of looking up those objects again for every relocation. The cost of building and searching a small hash table is much less than that of acquiring a spinlock, searching a radix tree and manipulating an atomic refcnt per relocation. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Don't post a downclocking task if the device is still active when the idle timer fires. A pathological process could queue up several seconds worth of processing and then go to sleep, during which time the idle timer would kick in and downclock the GPU. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 09 12月, 2010 2 次提交
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由 Chris Wilson 提交于
If the tail advances beyond the autoreport HEAD value, then we need to fallback to an uncached read of the HEAD register in order to ascertain the correct amount of remaining space in the ringbuffer. Reported-by: NFang, Xun <xunx.fang@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32259Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 David Flynn 提交于
The DisplayPort standard (1.1a) states that: The I2C-over-AUX Reply field is valid only when Native AUX CH Reply field is AUX_ACK (00). When Native AUX CH Reply field is not 00, then, I2C-over-AUX Reply field must be 00 and be ignored. This fixes broken EDID reading when using an active DisplayPort to duallink DVI converter. If the AUX CH replier chooses to defer the transaction, a short read occurs and erroneous data is returned as the i2c reply due to a lack of length checking and failure to check for AUX ACK. As a result, broken EDIDs can look like: 0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef 00: bc bc bc ff bc bc bc ff bc bc bc ac bc bc bc 45 ???.???.???????E 10: bc bc bc 10 bc bc bc 34 bc bc bc ee bc bc bc 4c ???????4???????L 20: bc bc bc 50 bc bc bc 00 bc bc bc 40 bc bc bc 00 ???P???.???@???. 30: bc bc bc 01 bc bc bc 01 bc bc bc a0 bc bc bc 40 ???????????????@ 40: bc bc bc 00 bc bc bc 00 bc bc bc 00 bc bc bc 55 ???.???.???.???U 50: bc bc bc 35 bc bc bc 31 bc bc bc 20 bc bc bc fc ???5???1??? ???? 60: bc bc bc 4c bc bc bc 34 bc bc bc 46 bc bc bc 00 ???L???4???F???. 70: bc bc bc 38 bc bc bc 11 bc bc bc 20 bc bc bc 20 ???8??????? ??? 80: bc bc bc ff bc bc bc ff bc bc bc ff bc bc bc ff ???.???.???.???. ... which can lead to: [drm:drm_edid_block_valid] *ERROR* EDID checksum is invalid, remainder [drm:drm_edid_block_valid] *ERROR* Raw EDID: <3>30 30 30 30 30 30 30 32 38 32 30 32 63 63 31 61 000000028202cc1a <3>28 00 02 8c 00 00 00 00 18 00 00 00 00 00 00 00 (............... <3>20 4c 61 73 74 20 62 65 61 63 6f 6e 3a 20 33 32 Last beacon: 32 <3>32 30 6d 73 20 61 67 6f 46 00 05 8c 00 00 00 00 20ms agoF....... <3>36 00 00 00 00 00 00 00 00 0c 57 69 2d 46 69 20 6.........Wi-Fi <3>52 6f 75 74 65 72 01 08 82 84 8b 96 24 30 48 6c Router......$0Hl <3>03 01 01 06 02 00 00 2a 01 00 2f 01 00 32 04 0c .......*../..2.. <3>12 18 60 dd 09 00 10 18 02 00 00 01 00 00 18 00 ..`............. Signed-off-by: NDavid Flynn <davidf@rd.bbc.co.uk> [ickle: fix up some surrounding checkpatch warnings] Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
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- 08 12月, 2010 11 次提交
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由 Linus Torvalds 提交于
Merge branches 'x86-fixes-for-linus', 'perf-fixes-for-linus' and 'sched-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86/pvclock: Zero last_value on resume * 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: perf record: Fix eternal wait for stillborn child perf header: Don't assume there's no attr info if no sample ids is provided perf symbols: Figure out start address of kernel map from kallsyms perf symbols: Fix kallsyms kernel/module map splitting * 'sched-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: nohz: Fix printk_needs_cpu() return value on offline cpus printk: Fix wake_up_klogd() vs cpu hotplug
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git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6由 Linus Torvalds 提交于
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/i915: i915 cannot provide switcher services. drm/radeon/kms: fix vram base calculation on rs780/rs880 drm/radeon/kms: fix formatting of vram and gtt info drm/radeon/kms: forbid big bo allocation (fdo 31708) v3 drm: Don't try and disable an encoder that was never enabled drm: Add missing drm_vblank_put() along queue vblank error path drm/i915/dp: Only apply the workaround if the select is still active drm/i915: Emit a request to clear a flushed and idle ring for unbusy bo drm/i915/lvds: Always restore panel-fitter when enabling the LVDS drm/i915/ringbuffer: Only print an error on the second attempt to reset head drm/i915: announce to userspace that the bsd ring is coherent agp/intel: Fix wrong kunmap in i830_cleanup() drm/i915: Factor in pixel-repeat in FDI M/N calculation drm/i915: Death to the unnecessary 64bit divide drm/i915: Clean conflicting modesetting registers upon init drm/i915: Apply a workaround for transitioning from DP on pipe B to HDMI. drm/i915: Always set the DP transcoder config to 8BPC.
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git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input由 Linus Torvalds 提交于
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input: Input: wacom - add new Bamboo PT (0xdb) Input: add input driver for polled GPIO buttons Input: turbografx - fix reference counting Input: synaptics - fix handling of 2-button ClickPads Input: wacom - add IDs for two new Bamboo PTs Input: document struct input_absinfo Input: add keycodes for touchpad on/off keys Input: usbtouchscreen - add support for LG Flatron T1710B
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由 Francisco Jerez 提交于
Signed-off-by: NFrancisco Jerez <currojerez@riseup.net> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Dave Airlie 提交于
it has a DSM but the switcher is done via WMI. Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 David Foley 提交于
Adds new Bamboo Pen & Touch model - Bamboo P & T Special Edition Medium (CTH661/L; Product ID = 0xdb). Tested-by: NTobias Verbeke <tobias.verbeke@gmail.com> Signed-off-by: NDavid Foley <favux.is@gmail.com> Acked-by: NPing Cheng <pingc@wacom.com> Signed-off-by: NDmitry Torokhov <dtor@mail.ru>
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由 Ben Skeggs 提交于
NVC0 will be able to share some of nv50's paths this way. This also makes it the card-specific vram code responsible for deciding if a given set of tile_flags is valid, rather than duplicating the allowed types in nv50_vram.c and nouveau_gem.c Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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