All the simple microblaze header files were adapted to use their
asm-generic implementations. These files are more simple and were quite
straightforward to change.

fb.h, vga.h and parport.h previously did not exist, using
the generic version makes it possible to build more drivers
successfully in allyesonfig.
Signed-off-by: NRemis Lima Baima <remis.developer@googlemail.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

The microblaze checksum code is mostly identical to
the asm-generic+lib version, so use that instead.
Signed-off-by: NRemis Lima Baima <remis.developer@googlemail.com>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Almost all of the ABI relevant header files now have generic
versions, so use those now in order to reduce the amount
of architecture specific code.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

For systems which do not define PHYS_OFFSET as 0 pfn_valid() may falsely
have returned 0 on most configurations.  Bug introduced by commit
752fbeb2e3555c0d236e992f1195fd7ce30e728d (linux-mips.org) rsp.
6f284a2c (kernel.org) titled "[MIPS]
FLATMEM: introduce PHYS_OFFSET."
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Move the cavium PCI files to the arch/mips/pci directory.  Also cleanup
comment formatting and code layout.  Code from pci-common.c, was moved
into other files.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NYoichi Yuasa <yuasa@linux-mips.org>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
Acked-by: NPavel Machek <pavel@ucw.cz>

If an o32 process generates a core dump on a 64 bit kernel, the core file
will not be correctly recognized. This is because ELF_CORE_COPY_REGS and
ELF_CORE_COPY_TASK_REGS are not correctly defined for o32 and will use
the default register set which would be CONFIG_64BIT in asm/elf.h.

So we'll switch to use the right register defines in this situation by
checking for WANT_COMPAT_REG_H and use the right defines of
ELF_CORE_COPY_REGS and ELF_CORE_COPY_TASK_REGS.

[Ralf: made ELF_CORE_COPY_TASK_REGS() bullet-proof against funny arguments.]
Signed-off-by: NYong Zhang <yong.zhang@windriver.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This revises the sync-4k so it will boot and operate since the removal of
expirelo from the timer code.
Signed-off-by: NTim Anderson <tanderson@mvista.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This is to move the gcmp_probe call to before the use of and selection of
the smp_ops functions. This allows malta with 1004K to work.
Signed-off-by: NTim Anderson <tanderson@mvista.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Most of the CMP support was added before, this mostly correct compile
problems but adds a platform specific translation for the interrupt number
based on cpu number.
Signed-off-by: NTim Anderson <tanderson@mvista.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This takes the current IPI interrupt assignment from the fix number of 4
to the number of CPUs defined in the system.
Signed-off-by: NTim Anderson <tanderson@mvista.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This patch extends the GIC interrupt handling beyond the current 32 bit
range as well as extending the number of interrupts based on the number
of CPUs.
Signed-off-by: NTim Anderson <tanderson@mvista.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Some CPUs implement mipsr2, but because they are a super-set of mips64r2 do
not define CONFIG_CPU_MIPS64_R2.  Cavium OCTEON falls into this category.
We would still like to use the optimized implementation, so since we have
already checked for CONFIG_CPU_MIPSR2, checking for CONFIG_64BIT instead of
CONFIG_CPU_MIPS64_R2 is sufficient.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NYoichi Yuasa <yyuasa@linux.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

[Ralf: I fixed up the numbering in the comment in scall64-n32.S.]
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NDmitri Vorobiev <dmitri.vorobiev@movial.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NJoe Perches <joe@perches.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This patch adds support for the Texas Instruments AR7 System-on-a-Chip.
It supports the TNETD7100, 7200 and 7300 versions of the SoC.
Signed-off-by: NMatteo Croce <matteo@openwrt.org>
Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NEugene Konev <ejka@openwrt.org>
Signed-off-by: NNicolas Thill <nico@openwrt.org>
Signed-off-by: NFlorian Fainelli <florian@openwrt.org>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Somewhat redundant since our atomic_t uses hashed-locks on 32-bit
anyway... Maybe we can clean those up to be generic too someday.
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

needed for perf_counters.
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

Reserve a syscall slot for sys_perf_counter_open.
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

The pa_pdc_cell struct can be kmalloc'd, so do that
instead.
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

The pa_pdc_cell struct can be kmalloc'd, so do that instead.
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

arch/parisc/mm/init.c: In function 'free_initmem':
381: warning: passing argument 1 of 'memset' makes pointer from integer without a cast
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

Unless I'm totally missing something get_fd_set32/set_fd_set32 are
completely unused.
Signed-off-by: NChristoph Hellwig <hch@lst.de>
Acked-by: NGrant Grundler <grundler@parisc-linux.org>
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

The TLB flushing functions on hppa, which causes PxTLB broadcasts on the system
bus, needs to be protected by irq-safe spinlocks to avoid irq handlers to deadlock
the kernel. The deadlocks only happened during I/O intensive loads and triggered
pretty seldom, which is why this bug went so long unnoticed.
Signed-off-by: NHelge Deller <deller@gmx.de>
[edited to use spin_lock_irqsave on UP as well since we'd been locking there
 all this time anyway, --kyle]
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

Rewrote timer_interrupt() to properly handle the "delayed!" case.

If we used floating point math to compute the number of ticks that had
elapsed since the last timer interrupt, it could take up to 12K cycles
(emperical!) to handle the interrupt. Existing code assumed it would
never take more than 8k cycles. We end up programming Interval Timer
to a value less than "current" cycle counter.  Thus have to wait until
Interval Timer "wrapped" and would then get the "delayed!" printk that
I moved below.

Since we don't really know what the upper limit is, I prefer to read
CR16 again after we've programmed it to make sure we won't have to
wait for CR16 to wrap.

Further, the printk was between reading CR16 (cycle couner) and writing CR16
(the interval timer). This would cause us to continue to set the interval
timer to a value that was "behind" the cycle counter. Rinse and repeat.
So no printk's between reading CR16 and setting next interval timer.

Tested on A500 (550 Mhz PA8600).
Signed-off-by: NGrant Grundler <grundler@parisc-linux.org>
Tested-by: NKyle McMartin <kyle@mcmartin.ca>
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

----
Kyle, Helge, and other parisc's,
Please test on 32-bit before committing.
I think I have it right but recognize I might not.

TODO: I wanted to use "do_div()" in order to get both remainder
and value back with one division op. That should help with the
latency alot but can be applied seperately from this patch.

thanks,
grant

>>>> I think this is what was intended? Note that this patch may affect
>>>> profiling.
>>> it really should be

> >>> -    if (likely(t1 & (sizeof(unsigned int)-1)) == 0) {
> >>> +    if (likely((t1 & (sizeof(unsigned int)-1)) == 0)) {

>>> randolph
Reported-by: NRoel Kluin <roel.kluin@gmail.com>
Signed-off-by: NRandolph Chung <tausq@parisc-linux.org>
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

This patch modifies parameter of au1x_counter1_read() from 'void' to 'struct
clocksource *cs', which fixes compile warning for incompatible parameter type.
Signed-off-by: NColy Li <coly.li@suse.de>
Signed-off-by: NHelge Deller <deller@gmx.de>
Cc: Ingo Molnar <mingo@elte.hu>
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

Fix this build error:
arch/parisc/math-emu/decode_exc.c:351: undefined reference to `printk'
Signed-off-by: NAlexander Beregalov <a.beregalov@gmail.com>
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

The defines and typedefs (hw_interrupt_type, no_irq_type, irq_desc_t) have
been kept around for migration reasons.  After more than two years it's
time to remove them finally.

This patch cleans up one of the remaining users.  When all such patches
hit mainline we can remove the defines and typedefs finally.

Impact: cleanup

Convert the last remaining users to struct irq_chip and remove the
define.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

Fix miscompilation in arch/parisc/kernel/irq.c:
123: warning: passing arg 1 of `cpumask_setall' from incompatible pointer type
141: warning: passing arg 1 of `cpumask_copy' from incompatible pointer type
300: warning: passing arg 1 of `cpumask_copy' from incompatible pointer type
357: warning: passing arg 2 of `cpumask_copy' from incompatible pointer type
Signed-off-by: NHelge Deller <deller@gmx.de>
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

There are two reasons to expose the memory *a in the asm:

1) To prevent the compiler from discarding a preceeding write to *a, and
2) to prevent it from caching *a in a register over the asm.

The change has had a few days testing with a SMP build of 2.6.22.19
running on a rp3440.

This patch is about the correctness of the __ldcw() macro itself.
The use of the macro should be confined to small inline functions
to try to limit the effect of clobbering memory on GCC's optimization
of loads and stores.
Signed-off-by: NDave Anglin <dave.anglin@nrc-cnrc.gc.ca>
Signed-off-by: NHelge Deller <deller@gmx.de>
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

Doing an IPI with local interrupts off triggers a warning. We
don't need to be quite so ridiculously paranoid. Also, clean up
a bit of the code a little.
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

The atomic operations on parisc are defined as macros. The macros
includes casts which disallows the use of some syntax elements and
produces error like this:

net/phonet/pep.c: In function 'pipe_rcv_status':
net/phonet/pep.c:262: error: lvalue required as left operand of assignment

The patch removes this superfluous casts.
Signed-off-by: NBastian Blank <waldi@debian.org>
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

Signed-off-by: NAlexander Beregalov <a.beregalov@gmail.com>
Acked-by: NMatthew Wilcox <willy@linux.intel.com>
Acked-by: NGrant Grundler <grundler@parisc-linux.org>
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>

Generic compat handlers look appropriate, so use those.
Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>