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  1. 02 10月, 2015 6 次提交
  3. 27 9月, 2015 2 次提交
  5. 07 7月, 2015 2 次提交
  7. 14 5月, 2015 1 次提交
  9. 30 4月, 2015 7 次提交
  11. 10 4月, 2015 1 次提交
  13. 08 4月, 2015 1 次提交
  15. 04 4月, 2015 1 次提交
  17. 20 3月, 2015 1 次提交
    • V
      usb: dwc2: avoid leaking DMA channels on disconnection · 7252f1bf
      由 Vincent Palatin 提交于 
      When the HCD is disconnected, the DMA transfers still in-flight were cleaned-up
but the count of available DMA channels (e.g. available_host_channels) was not
reset.
The pool of DMA channels can be depleted when doing unclean
disconnection of USB peripherals, and reaches the point where no
transfer was possible until the next reboot/reload of the driver.

Tested by putting a programmable USB mux on the port and randomly
plugging/unpluging a USB HUB with USB mass-storage key, USB-audio and
USB-ethernet dongle connected to its downstream ports, and also doing the
disconnection early while the devices are still enumerating to get more URBs
in-flight.
After the patch, the devices are still enumerating after thousands of cycles,
while the port was totally dead before.
Signed-off-by: NVincent Palatin <vpalatin@chromium.org>
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>
      7252f1bf
  19. 31 1月, 2015 2 次提交
  21. 25 1月, 2015 1 次提交
  23. 20 1月, 2015 2 次提交
  25. 15 11月, 2014 3 次提交
  27. 12 11月, 2014 1 次提交
  29. 20 9月, 2014 1 次提交
    • P
      usb: dwc2: handle DMA buffer unmapping sanely · 5dce9555
      由 Paul Zimmerman 提交于 
      The driver's handling of DMA buffers for non-aligned transfers
was kind of nuts. For IN transfers, it left the URB DMA buffer
mapped until the transfer completed, then synced it, copied the
data from the bounce buffer, then synced it again.

Instead of that, just call usb_hcd_unmap_urb_for_dma() to unmap
the buffer before starting the transfer. Then no syncing is
required when doing the copy. This should also allow handling of
other types of mappings besides just dma_map_single() ones.

Also reduce the size of the bounce buffer allocation for Isoc
endpoints to 3K, since that's the largest possible transfer size.

Tested on Raspberry Pi and Altera SOCFPGA.
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      5dce9555
  31. 05 2月, 2014 1 次提交
  33. 14 1月, 2014 1 次提交
  35. 09 12月, 2013 2 次提交
  37. 04 12月, 2013 1 次提交
  39. 26 11月, 2013 1 次提交
  41. 29 10月, 2013 1 次提交
  43. 26 9月, 2013 1 次提交
    • D
      staging: dwc2: add microframe scheduler from downstream Pi kernel · 20f2eb9c
      由 Dom Cobley 提交于 
      The transfer scheduler in the dwc2 driver is pretty basic, not to
mention buggy. It works fairly well with just a couple of devices
plugged in, but if you add, say, multiple devices with periodic
endpoints, the scheduler breaks down and can't even enumerate all
the devices.

To improve this, import the "microframe scheduler" patch from the
driver in the downstream Raspberry Pi kernel, which is based on
the Synopsys vendor driver. The original patch came from Denx
(http://git.denx.de/?p=linux-denx.git) and was commited to the
raspberrypi.org git tree by "popcornmix" (Dom Cobley).

I have added a driver parameter for this, enabled by default, in
case anyone has problems with it and needs to disable it. I don't
think we should add a DT binding for that, though, since I plan
to remove the option once any bugs are fixed.

[raspberrypi.org patch from Dom Cobley]
Signed-off-by: NDom Cobley <popcornmix@gmail.com>
[adapted to dwc2 driver by Paul Zimmerman]
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      20f2eb9c