提交 · 05e34754518b6a90d5c392790c032575fab12d66 · openeuler / raspberrypi-kernel

15 3月, 2011 1 次提交

ARM: 6806/1: irq: introduce entry and exit functions for chained handlers · 10a8c383

由 Will Deacon 提交于 3月 14, 2011

Some chained IRQ handlers are written to cope with primary chips of
potentially different flow types. Whether this a sensible thing to do
is a point of contention.

This patch introduces entry/exit functions for chained handlers which
infer the flow type of the primary chip as fasteoi or level-type by
checking whether or not the ->irq_eoi function pointer is present and
calling back to the primary chip as necessary. Other methods of flow
control are not considered.
Acked-by: NThomas Gleixner <tglx@linutronix.de>
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

10a8c383

11 3月, 2011 2 次提交

ARM: 6781/1: Thumb-2: Work around buggy Thumb-2 short branch relocations in gas · 6f685c5c

由 Dave Martin 提交于 3月 03, 2011

Various binutils versions can resolve Thumb-2 branches to
locally-defined, preemptible global symbols as short-range "b.n"
branch instructions.

This is a problem, because there's no guarantee the final
destination of the symbol, or any candidate locations for a
trampoline, are within range of the branch.  For this reason, the
kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
relocation in modules at all, and it makes little sense to add
support.

The symptom is that the kernel fails with an "unsupported
relocation" error when loading some modules.

Until fixed tools are available, passing
-fno-optimize-sibling-calls to gcc should prevent gcc generating
code which hits this problem, at the cost of a bit of extra runtime
stack usage in some cases.

The problem is described in more detail at:
    https://bugs.launchpad.net/binutils-linaro/+bug/725126

Only Thumb-2 kernels are affected.

This patch adds a new CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11 config
option which adds -fno-optimize-sibling-calls to CFLAGS_MODULE
when building a Thumb-2 kernel.
Signed-off-by: NDave Martin <dave.martin@linaro.org>
Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

6f685c5c

ARM: 6747/1: P2V: Thumb2 support · b511d75d

由 Nicolas Pitre 提交于 2月 21, 2011

Adding Thumb2 support to the runtime patching of the virt_to_phys and
phys_to_virt opcodes.

Tested both the 8-bit and the 16-bit fixups, using different placements
in memory to exercize all code paths.
Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Reviewed-by: NDave Martin <dave.martin@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

b511d75d

10 3月, 2011 5 次提交

ARM: 6798/1: aout-core: zero thread debug registers in a.out core dump · 23bfdacf

由 Will Deacon 提交于 3月 10, 2011

The removal of the single-step emulation from ptrace on ARM means that
thread_struct no longer has software breakpoint fields in its debug
member.

This patch fixes the a.out core dump code so that the debug registers
are zeroed rather than trying to copy from non-existent fields.

Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: NBryan Wu <bryan.wu@canonical.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

23bfdacf

ARM: 6796/1: Footbridge: Fix I/O mappings for NOMMU mode · 6fa85e5c

由 Stepan Moskovchenko 提交于 3月 10, 2011

Use the correct I/O address definitions for Footbridge
peripherals when the kernel is compiled without MMU
support.
Signed-off-by: NStepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

6fa85e5c

ARM: 6784/1: errata: no automatic Store Buffer drain on Cortex-A9 · 5dab26af

由 Will Deacon 提交于 3月 04, 2011

On revisions of the Cortex-A9 prior to r2p0, the Store Buffer does not
have any automatic draining mechanism and therefore a livelock may occur
if an external agent continuously polls a memory location waiting to
observe an update.

This workaround defines cpu_relax() as smp_mb(), preventing correctly
written polling loops from denying visibility of updates to memory.
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

5dab26af

ARM: 6772/1: errata: possible fault MMU translations following an ASID switch · fcbdc5fe

由 Will Deacon 提交于 2月 28, 2011

On the r2p* and r3p* versions of the Cortex-A9, a speculative memory
access may cause a page table walk which starts prior to an ASID switch
but completes afterwards. This can populate the micro-TLB with a stale
entry which may be hit with the new ASID.

This workaround places two dsb instructions in the mm switching code so
that no page table walks can cross the ASID switch.
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

fcbdc5fe

ARM: 6776/1: mach-ux500: activate fix for errata 753970 · 6e266b20

由 Linus Walleij 提交于 3月 01, 2011

This applies errata fix 753970 for all ux500 platforms. All
current ASICs suffer from this. If the problem is resolved in
later ASICs, the errata selection can be pushed down to other
Kconfig options.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

6e266b20

09 3月, 2011 19 次提交

ARM: 6794/1: SPEAr: Append UL to device address macros. · 981a95d3

由 Shiraz Hashim 提交于 3月 07, 2011

Reviewed-by: NStanley Miao <stanley.miao@windriver.com>
Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: NRajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

981a95d3

ARM: 6793/1: SPEAr: Remove unused *_SIZE macros from spear*.h files · 8fc4ef45