Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@ti.com>

There is an unfortunate difference in return values between spi_write()
and i2c_master_send() so we need an adaptor function to translate.
Reported-by: NLars-Peter Clausen <lars@metafoo.de>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@ti.com>

do_spi_write() is just an open coded copy of do_spi_write() so we can
delete it and just call spi_write() directly.  Indeed, as a result of
recent refactoring all the SPI write functions are just very long
wrappers around spi_write() which don't add anything except for some
pointless copies so we can just use spi_write() as the hw_write
operation directly. It should be as type safe to do this as it is to do
the same thing with I2C and it saves us a bunch of code.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@ti.com>

snd_soc_4_12_spi_write() contains a byte swap. Since this code was written
for an Analog CODEC on a Blackfin reference board it appears that this is
done because while Blackfin is little endian the CODEC is big endian (as
are most CODECs).

Push this up into the generic 4x12 write function and use cpu_to_be16() to
do the byte swap so things are more regular and things work on both CPU
endiannesses.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@ti.com>

Currently we'll force all registers to fit in 8 bits before passing
down to the I/O function. Looks like a cut'n'paste bug.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@ti.com>

If we specifically want to write a block of data to the hw bypassing the
cache, then allow this to happen inside snd_soc_hw_bulk_write_raw().
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@ti.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

`type` parameter is not longer used in `snd_soc_codec_set_cache_io`,
so remove this line.
Signed-off-by: NLu Guanqun <guanqun.lu@intel.com>
Acked-by: NLiam Girdwood <lrg@ti.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Lines should be less than 80 columns.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

We don't need to log every I2C transfer, and certainly not at error level.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

This patch fixes to avoid compile error when ASoC codec doesn't use I2C
nor SPI on snd_soc_hw_bulk_write_raw().
Signed-off-by: NSeungwhan Youn <sw.youn@samsung.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

When syncing the cache, if the driver has given us a writable_register()
callback, use it to check if we are syncing a non-writable register
and if so warn the user.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@ti.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@ti.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

By using struct snd_soc_reg_access for the read/write/vol attributes
of the registers, we provide callbacks that automatically determine whether
a given register is readable/writable or volatile.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@ti.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

These functions fail with -EINVAL if the corresponding callbacks
are not implemented.  Change them to return -ENOSYS as it is more
appropriate for unimplemented callbacks.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@ti.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

The handling of all snd_soc_x_y_spi_write() functions is similar.
Create a separate function and update all callers to use it.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@ti.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

The handling of all snd_soc_x_y_read() functions is similar.
Factor it out into a separate function and update all callers.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@ti.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

The handling of all snd_soc_x_y_write() functions is similar.
Factor it out into a separate function and update all functions
to use it.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@ti.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

As it has become more common to have to write firmware or similar
large chunks of data to the hardware, add a function to perform
raw bulk writes that bypass the cache.  This only handles volatile
registers as we should avoid getting out of sync with the actual
cache.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@ti.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

The handling of all snd_soc_x_y_read_i2c() functions is similar.
Make a generic I2C read function and update all callers to use it.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@ti.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

The patch c358e640 "ASoC: soc-cache: Add trace event for
snd_soc_cache_sync()" introduced a dereference of "codec->cache_ops"
before we had checked it for NULL.

I pulled the check forward, and then pulled everything in an indent
level.
Signed-off-by: NDan Carpenter <error27@gmail.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

This patch makes it easy to see when the syncing process begins and
ends.  You can also enable the snd_soc_reg_write tracepoint to see
which registers are being synced.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Incorporate the use of the cache_bypass functionality in the
syncing functions.  The snd_soc_flat_cache_sync() need not be
hooked as there is no performance benefit from using the
cache_bypass option.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

This is primarily needed to avoid writing back to the cache
whenever we are syncing the cache with the hardware.  This gives a
performance benefit especially for large register maps.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

For common scenarios, device drivers can provide a table of all the
registers that are at least either readable/writable/volatile.  The idea
is that if a register lookup fails, all of its read/write/vol members
will be zero and will be treated as default.  This also reduces the
size of the register access array.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Simplify the use of reg_size, by calculating it once and storing it in
the codec structure for later reference.  The value of reg_size is
reg_cache_size * reg_word_size.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

With the addition of the cache fallback functionality, it is necessary
to ensure that if the register defaults cache was marked as __devinitconst
and the LZO compression is not compiled in the kernel, the fallback to
flat compression will still use a copy of the defaults cache.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Use Takashi's clean up code to make the cache manipulation code more
readable.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

The size of the lzo syncing bitmap was incorrectly set to the size
of the cache times the word size, however, the correct size is the
size of the cache.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Make LZO cache compression optional as it pulls in the kernel wide LZO
implementation and rbtree compression is generally more efficient for
typical register maps, especially in terms of CPU performance.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>

This makes it easier to make cache types build time configurable as we
don't have a hard dependency on a given cache being built in.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>

Remove redundant parentheses/spaces in the use of the sizeof
operator.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Added an optional name member to snd_soc_cache_ops to enable more
sensible diagnostic messages during cache init, exit and sync.

Remove redundant newline in source code.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Allow the CODEC driver structure to be marked const by making all
the APIs that use it do so.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>

Make sure to use codec->reg_def_copy instead of codec_drv->reg_cache_default
wherever necessary.  This change is necessary because in the next patch we
move the cache initialization code outside snd_soc_register_codec() and by that
time any data marked as __devinitconst such as the original reg_cache_default
array might have already been freed by the kernel.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

We need to keep a copy of the compress_type supplied by the codec driver
so that we can override it if necessary with whatever the machine driver
has provided us with.  The reason for not modifying the codec->driver
struct directly is that ideally we'd like to keep it const.

Adjust the code in soc-cache and soc-core to make use of the compress_type
member in the snd_soc_codec struct.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

We shouldn't be assigning to the driver structure (which really ought
to be const, further patch to follow) though there's unlikely to be any
actual problem except in the unlikely case that two devices with the
same driver but different bus types appear in the same system.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>

The bitmap_zero() nbits argument was improperly set to reg_size
but the underlying buffer was bmp_size long.  This caused the memset
to zero past the end of the allocated buffer and into the kernel heap
causing strange kernel crashes sometimes by overwriting critical
kernel structures.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Ensure that we report any errors encountered during reads/writes
in the cache syncing functions.

Remove redundant newline in the source code.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

This patch adds support for rbtree compression when storing the
register cache.  It does this by not adding any uninitialized registers
(those whose value is 0).  If any of those registers is written
with a nonzero value they get added into the rbtree.

Consider a sample device with a large sparse register map.  The
register indices are between [0, 0x31ff].  An array of 12800 registers
is thus created each of which is 2 bytes.  This results in a 25kB
region.  This array normally lives outside soc-core, normally in the
driver itself.  The original soc-core code would kmemdup this region
resulting in 50kB total memory.  When using the rbtree compression
technique and __devinitconst on the original array the figures are
as follows.  For this typical device, you might have 100 initialized
registers, that is registers that are nonzero by default.  We build
an rbtree with 100 nodes, each of which is 24 bytes.  This results
in ~2kB of memory.  Assuming that the target arch can freeup the
memory used by the initial __devinitconst array, we end up using
about ~2kB bytes of actual memory.  The memory footprint will increase
as uninitialized registers get written and thus new nodes created in
the rbtree.  In practice, most of those registers are never changed.
If the target arch can't freeup the __devinitconst array, we end up
using a total of ~27kB.  The difference between the rbtree and the LZO
caching techniques, is that if using the LZO technique the size of
the cache will increase slower as more uninitialized registers get
changed.
Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>