The display controller found on Tegra30 SoCs is backwards-compatible
with the one on Tegra20 SoCs.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add device tree entries for the 3 USB controllers and PHYs and
enable the third controller on Cardhu and Beaver boards.

Fix VBUS regulator entries on Beaver. The GPIO pins were wrong.
Also, internal pullups need to be enabled on those pins.
Signed-off-by: NTuomas Tynkkynen <ttynkkynen@nvidia.com>
Tested-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Instead of evenly splitting the 512 MiB area between prefetchable and
non-prefetchable memory spaces, increase the prefetchable memory space
to 384 MiB while at the same time decreasing the non-prefetchable memory
space to 128 MiB. This is a more useful default as most PCIe devices
require more prefetchable than non-prefetchable memory.
Signed-off-by: NJay Agarwal <jagarwal@nvidia.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add the top-level pcie-controller node for the Tegra30 SoC. Tegra30 has
three root ports that can use different lane layouts.
Signed-off-by: NJay Agarwal <jagarwal@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Use the Tegra30 CAR binding header (tegra30-car.h) to replace magic
numbers in the device tree. For example,

-               clocks = <&tegra_car 28>;
+               clocks = <&tegra_car CLK_HOST1X>;
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
[swarren, updated since tegra30-car.h moved for consistency]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Use the GIC and standard IRQ binding defines in all IRQ specifiers.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Use TEGRA_GPIO() macro to name all GPIOs referenced by GPIO properties,
and some interrupts properties. Use standard GPIO flag defines too.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Replace /include/ (dtc) with #include (C pre-processor) for all Tegra DT
files, so that gcc -E handles the entire include tree, and hence any of
those files can #include some other file e.g. for constant definitions.

This allows future use of #defines and header files in order to define
names for various constants, such as the IDs and flags in GPIO
specifiers. Use of those features will increase the readability of the
device tree files.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

We should be defining the PWM nodes with status as "disabled" in the
chip-specific dtsi file, since we don't know whether specific boards
will use the PWM or not. This patch fixes the PWM node status for
Tegra20 and Tegra30.

Also fixed the one user of PWM, which is the Tegra20 medcom-wide board,
so that PWM is set to "okay" in the board-specific dts file.
Signed-off-by: NAndrew Chew <achew@nvidia.com>
[swarren: in medcom-wide: fixed node sort order, removed duplicate pwm:
label, fixed syntax error]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Adding the bindings of the clock source of PMC in DT.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Fix typo on register address of slink3 controller where register
address is wrongly set as 0x7000d480 but it is 0x7000d800.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The PMC HW is not 100% compatible across all Tegra series. We need to
specify them in DT.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The new clockframework introduced DT IDs for each clock. To be able to remove
the device registrations, this driver needs to be updated to use the DT IDs.
Note that the actual removal of the clk_register_clkdev() calls will be done
in a later series.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

As DT support for clocks and smp_twd is enabled, add clock entry
for smp_twd clock to DT.

This fixes the following error while booting the kernel:
smp_twd: clock not found -2
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
[swarren: include kernel log spew that this fixes]
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Currently, the serial nodes define both a clock-frequency and a clocks
property. We should not provide both, since they might conflict.

In practice, this also causes problems since the of_serial driver uses
the clock-frequency property in preference to the clocks property, and
hence doesn't clk_prepare_enable() the clock, which may then leave it
with no known users, and hence the common clock framework will disable
it, thus breaking the port, which is usually the console.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Use functional name for DT entry instead of h/w name.
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

NVIDIA's Tegra SoCs have the matrix keyboard controller which
supports 16x8 type of matrix. The number of rows and columns
are configurable.

Add DT entry for KBC controller.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
[swarren: added clocks property]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This ensures nodes are sorted in order of reg address. This makes it
easier to compare against e.g. the U-Boot device trees, and is simply
consistent and clean.

While we're at it, remove the unit address from the cache-controller
node name, since it's unique without it.
Reported-by: NAllen Martin <amartin@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add APB DMA requestor and serial aliases for serial controller.
There will be two serial driver i.e. 8250 based simple serial driver
and APB DMA based serial driver for higher baudrate and performace.

The simple serial driver get enabled with compatible nvidia,tegra20-uart
and APB DMA based driver will get enabled with compatible
nvidia,tegra20-hsuart.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

tegra30 gpio controller is not compatible with the tegra20 due to
their bank stride i.e. Tegra20 bank stride is 0x80 where Tegra30
bank stride is 0x100.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
[swarren: fixed typo syntax error]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add clock information to device nodes.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
[swarren: added second clock to 3d node]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The device tree binding models Tegra30 CAR (Clock And Reset)
as a single monolithic clock provider.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
[swarren: fixed typo in binding doc]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add CPU node for Tegra30.
Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
Reviewed-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This will allow timer.c to use twd_local_timer_of_register(), and
hence not need to hard-code the TWD address or IRQ.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The Tegra RTC maintains seconds and milliseconds counters, and five alarm
registers. The alarms and other interrupts may wake the system from
low-power state.

Define a DT binding for this HW module, and add the module into the Tegra
device tree files.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The Tegra timer provides a number of 29-bit timer channels, a single
32-bit free running counter, and in the Tegra30 variant, 5 watchdog modules.
The first two channels may also trigger a legacy watchdog reset.

Define a DT binding for this HW module, and add the module into the Tegra
device tree files.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add the host1x node along with its children to the Tegra30 DTSI. Board-
specific DTS files are expected to enable the available outputs and
complement the device tree with data specific to the hardware.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add slink controller details in the dts file of
Tegra20 and Tegra30.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add L2 cache controller binding into DT for Tegra.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The reg property contains <base length> not <base last_offset>. Fix
the length values to be length not last_offset.

Cc: stable@vger.kernel.org
Signed-off-by: NPritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

PWM devices can be referenced in the DT by phandle and per-chip index.
In order for this to work properly, the PWM controller needs to have a
label attached to it.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add auxdata to instantiate the PWFM controller from a device tree,
include the corresponding nodes in the dtsi files for Tegra 20 and
Tegra 30 and add binding documentation.
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>

This patches fixes some status = "disable" strings to "disabled", the correct
way of disabling nodes in the devicetree.

Just the tegra part here. Everything else goes via other patches and trees.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Use a more plain english name.
Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com>
[swarren: remove redundant unit address from tegra30.dtsi change]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

In tegra*.dtsi, set status="disable" for all HW modules that the board
design may choose not to use. Update all boards to specifically enable
any of those modules that are useful by setting status="okay".

This makes board files say which features they do use, rather than which
they don't, which feels more logical. It also makes the .dts files
slightly smaller, at least for existing content.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

Put properties in order compatible, reg, interrupts, then anything else
the node has.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

Sort the nodes according to the following rules:
* First, any overrides for properties or nodes created by included files,
  in the order they appeared in the include file.
* Second, any nodes with a reg property, in numerical order.
* Third, any nodes without a reg property, in alphabetical order of node
  name.

The second sorting rule at least will probably help if/when we need to
explicitly insert nodes for the various busses in Tegra; that will just
be an indentation change rather than also a node re-ordering.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

Place each reg "entry" on its own line, and wrap the whole list in
<> rather than each individual entry.

The convention chosen here is slightly arbitrary, but is not consistent
throughout all Tegra files.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>