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  1. 07 5月, 2018 1 次提交
  3. 02 5月, 2018 1 次提交
  5. 27 4月, 2018 4 次提交
    • H
      libata: Apply NOLPM quirk for SanDisk SD7UB3Q*G1001 SSDs · 184add2c
      由 Hans de Goede 提交于 
      Richard Jones has reported that using med_power_with_dipm on a T450s
with a Sandisk SD7UB3Q256G1001 SSD (firmware version X2180501) is
causing the machine to hang.

Switching the LPM to max_performance fixes this, so it seems that
this Sandisk SSD does not handle LPM well.

Note in the past there have been bug-reports about the following
Sandisk models not working with min_power, so we may need to extend
the quirk list in the future: name - firmware
Sandisk SD6SB2M512G1022I   - X210400
Sandisk SD6PP4M-256G-1006  - A200906

Cc: stable@vger.kernel.org
Cc: Richard W.M. Jones <rjones@redhat.com>
Reported-and-tested-by: NRichard W.M. Jones <rjones@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NTejun Heo <tj@kernel.org>
      184add2c
    • H
      libata: Apply NOLPM quirk for SAMSUNG MZMPC128HBFU-000MV SSD · b5b4d3a5
      由 Hans de Goede 提交于 
      Kevin Shanahan reports the following repeating errors when using LPM,
causing long delays accessing the disk:

  Apr 23 10:21:43 link kernel: ata1.00: exception Emask 0x0 SAct 0x0 SErr 0x50000 action 0x6 frozen
  Apr 23 10:21:43 link kernel: ata1: SError: { PHYRdyChg CommWake }
  Apr 23 10:21:43 link kernel: ata1.00: failed command: WRITE DMA
  Apr 23 10:21:43 link kernel: ata1.00: cmd ca/00:08:60:5d:cd/00:00:00:00:00/e1 tag 9 dma 4096 out
                                        res 50/01:01:01:00:00/00:00:00:00:00/00 Emask 0x4 (timeout)
  Apr 23 10:21:43 link kernel: ata1.00: status: { DRDY }
  Apr 23 10:21:43 link kernel: ata1.00: error: { AMNF }
  Apr 23 10:21:43 link kernel: ata1: hard resetting link
  Apr 23 10:21:43 link kernel: ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
  Apr 23 10:21:43 link kernel: ata1.00: configured for UDMA/133
  Apr 23 10:21:43 link kernel: ata1: EH complete

These go away when switching from med_power_with_dipm to medium_power.

This is somewhat weird as the PM830 datasheet explicitly mentions DIPM
being supported and the idle power-consumption is specified with DIPM
enabled.

There are many OEM customized firmware versions for the PM830, so for now
lets assume this is firmware version specific and blacklist LPM based on
the firmware version.

Cc: Kevin Shanahan <kevin@shanahan.id.au>
Reported-by: NKevin Shanahan <kevin@shanahan.id.au>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NTejun Heo <tj@kernel.org>
      b5b4d3a5
    • E
      ata: ahci: mvebu: override ahci_stop_engine for mvebu AHCI · daa2e3bd
      由 Evan Wang 提交于 
      There is an issue(Errata Ref#226) that the SATA can not be
detected via SATA Port-MultiPlayer(PMP) with following
error log:
  ata1.15: PMP product ID mismatch
  ata1.15: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
  ata1.15: Port Multiplier vendor mismatch '0x1b4b'!='0x0'
  ata1.15: PMP revalidation failed (errno=-19)

After debugging, the reason is found that the value Port-x
FIS-based Switching Control(PxFBS@0x40) become wrong.
According to design, the bits[11:8, 0] of register PxFBS
are cleared when Port Command and Status (0x18) bit[0]
changes its value from 1 to 0, i.e. falling edge of Port
Command and Status bit[0] sends PULSE that resets PxFBS
bits[11:8; 0].
So it needs a mvebu SATA WA to save the port PxFBS register
before PxCMD ST write and restore it afterwards.

This patch implements the WA in a separate function of
ahci_mvebu_stop_engine to override ahci_stop_gngine.
Signed-off-by: NEvan Wang <xswang@marvell.com>
Cc: Ofer Heifetz <oferh@marvell.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: NTejun Heo <tj@kernel.org>
      daa2e3bd
    • E
      libahci: Allow drivers to override stop_engine · fa89f53b
      由 Evan Wang 提交于 
      Marvell armada37xx, armada7k and armada8k share the same
AHCI sata controller IP, and currently there is an issue
(Errata Ref#226)that the SATA can not be detected via SATA
Port-MultiPlayer(PMP). After debugging, the reason is
found that the value of Port-x FIS-based Switching Control
(PxFBS@0x40) became wrong.
According to design, the bits[11:8, 0] of register PxFBS
are cleared when Port Command and Status (0x18) bit[0]
changes its value from 1 to 0, i.e. falling edge of Port
Command and Status bit[0] sends PULSE that resets PxFBS
bits[11:8; 0].
So it needs save the port PxFBS register before PxCMD
ST write and restore the port PxFBS register afterwards
in ahci_stop_engine().

This commit allows drivers to override ahci_stop_engine
behavior for use by the Marvell AHCI driver(and potentially
other drivers in the future).
Signed-off-by: NEvan Wang <xswang@marvell.com>
Cc: Ofer Heifetz <oferh@marvell.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: NTejun Heo <tj@kernel.org>
      fa89f53b
  7. 10 4月, 2018 1 次提交
  9. 29 3月, 2018 1 次提交
    • R
      ahci: imx: add the imx8qm ahci sata support · 027fa4de
      由 Richard Zhu 提交于 
      - There are three PHY lanes on iMX8QM, and can be
  used in the following three cases
    1. a two lanes PCIE_A, and a single lane SATA.
    2. a single lane PCIE_A, a single lane PCIE_B
    and a single lane SATA.
    3. a two lanes PCIE_A, and a single lane PCIE_B.
  The configuration of the iMX8QM AHCI SATA is relied
  on the usage of PCIE ports in the case 1 and 2.
  Use standalone iMX8 AHCI SATA probe and enable
  functions to enable iMX8QM AHCI SATA support.
- To save power consumption, PHY CLKs can be gated
  off after the configurations are done.
- The impedance ratio should be configured refer to
  differnet REXT values.
  0x6c <--> REXT value is 85Ohms
  0x80 (default value) <--> REXT value is 100Ohms.
  In general, REXT value should be 85ohms in standalone
  PCIE HW board design, and 100ohms in SATA standalone
  HW board design.
  When the PCIE and the SATA are enabled simultaneously
  in the HW board design. The REXT value would be set
  to 85ohms.
  Configure the SATA PHY impedance ratio to 0x6c in
  default.
Signed-off-by: NRichard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NTejun Heo <tj@kernel.org>
      027fa4de
  11. 27 3月, 2018 1 次提交
  13. 26 3月, 2018 2 次提交
  15. 21 3月, 2018 1 次提交
  17. 19 3月, 2018 5 次提交
  19. 14 3月, 2018 8 次提交
  21. 12 3月, 2018 1 次提交
  23. 05 3月, 2018 1 次提交
  25. 02 3月, 2018 3 次提交
  27. 21 2月, 2018 1 次提交
  29. 18 2月, 2018 8 次提交
  31. 13 2月, 2018 1 次提交