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  1. 26 9月, 2013 3 次提交
    • D
      mmc: sdhci-esdhc-imx: add sd3.0 SDR clock tuning support · 0322191e
      由 Dong Aisheng 提交于 
      Freescale i.MX6Q/DL uSDHC clock tuning progress is a little different from
the standard tuning process defined in host controller spec v3.0.
Thus we use platform_execute_tuning instead of standard sdhci tuning.

The main difference are:
1) not only generate Buffer Read Ready interrupt when tuning is performing.
   It generates all other DATA interrupts like the normal data command.
2) SDHCI_CTRL_EXEC_TUNING is not automatically cleared by HW,
   instead it's controlled by SW.
3) SDHCI_CTRL_TUNED_CLK is not automatically set by HW,
   it's controlled by SW.
4) the clock delay for every tuning is set by SW.
Signed-off-by: NDong Aisheng <b29396@freescale.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NChris Ball <cjb@laptop.org>
      0322191e
    • D
      mmc: sdhci-esdhc-imx: support real clock on and off for imx6q · fed2f6e2
      由 Dong Aisheng 提交于 
      The signal voltage switch flow requires to shutdown and output
clock in a specific sequence according to standard host controller
v3.0 spec. In that timing, the card must really receive clock or not.

However, for i.MX6Q, the uSDHC will not output clock even the clock
is enabled until there is command or data in transfer on the bus,
which will then cause singal voltage switch always to fail.

For i.MX6Q, we clear ESDHC_VENDOR_SPEC_FRC_SDCLK_ON bit to let
controller to gate off clock automatically and set that bit
to force clock output if clock is on.

This is required by SD3.0 support.
Signed-off-by: NDong Aisheng <b29396@freescale.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NChris Ball <cjb@laptop.org>
      fed2f6e2
    • D
      mmc: sdhci-esdhc: move common esdhc_set_clock to platform driver · d31fc00a
      由 Dong Aisheng 提交于 
      We need a lot of imx6 specific things into common esdhc_set_clock
for support SD3.0 and eMMC DDR mode which is not needed for power pc
platforms, so esdhc_set_clock seems not so common anymore.

Instead of keeping add platform specfics things into this common API,
we choose to move that code into platform driver itself to handle.
This can also exclude the dependency between imx and power pc on this
headfile and is easy for maintain in the future.
Signed-off-by: NDong Aisheng <b29396@freescale.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NChris Ball <cjb@laptop.org>
      d31fc00a
  3. 25 8月, 2013 1 次提交
  5. 27 6月, 2013 2 次提交
  7. 31 5月, 2013 1 次提交
  9. 27 5月, 2013 2 次提交
    • L
      mmc: sdhci-esdhc-imx: fix multiblock reads on i.MX53 · 361b8482
      由 Lucas Stach 提交于 
      The eSDHC controller on the i.MX53 needs an additional, non spec
compliant CMD12 after a multiblock read with a predefined number of
blocks. Otherwise the internal state machine won't go back to the
idle state.

This commit effectively reverts 5b6b0ad6 (mmc: sdhci-esdhc-imx:
fix for mmc cards on i.MX5), which fixed part of the problem by
making multiblock reads work, however this fix was not sufficient
when multi- and singleblock reads got intermixed.

This implements the recommended workaround (Freescale i.MX Reference
Manual, section 29.6.8 "Multi-block Read") by manually sending a
CMD12 with the RSPTYP bits cleared.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NChris Ball <cjb@laptop.org>
      361b8482
    • M
      mmc: sdhci-esdhc-imx: Fix SDIO interrupts · f6825748
      由 Martin Fuzzey 提交于 
      Currently SDIO interrupts do not work on i.MX53 and maybe others.

This was observed with a Marvell 8787 based SDIO wifi adapter
using the mwifiex driver and firmware from the Marvell git
repository.
The symptom was a timeout after firmware download.

Observing the SDIO_DAT1 line showed that an interrupt was requested
(level 0) but no interrupt was generated in software, the line
stayed low until a timeout ocurred and the card was reset.

There is a Freescale errata
	ENGcm11186 "eSDHC misses SDIO interrupt when CINT is disabled"

The workaround suggested by this errata is already implemented and
involves clearing and then setting the D3CD bit in the host control
register [see esdhc_writel_le()]

However, when esdhc_writeb_le() is later used to write to
SDHCI_HOST_CONTROL it always resets the D3CD bit.

To fix this simply add the D3CD bit to the set of bits
not modified by esdhc_writeb_le().
Signed-off-by: NMartin Fuzzey <mfuzzey@parkeon.com>
Signed-off-by: NChris Ball <cjb@laptop.org>
      f6825748
  11. 23 3月, 2013 2 次提交
  13. 25 2月, 2013 9 次提交
  15. 12 2月, 2013 2 次提交
  17. 28 1月, 2013 2 次提交
  19. 07 12月, 2012 1 次提交
  21. 29 11月, 2012 3 次提交
  23. 14 9月, 2012 1 次提交
  25. 02 9月, 2012 1 次提交
  27. 23 7月, 2012 1 次提交
  29. 15 5月, 2012 1 次提交
  31. 11 5月, 2012 1 次提交
  33. 25 4月, 2012 1 次提交
    • S
      mmc sdhc i.MX: do not depend on grouped clocks · 52dac615
      由 Sascha Hauer 提交于 
      the current i.MX clock support groups together unrelated clocks
to a single clock which is then used by the driver. This can't
be accomplished with the generic clock framework so we instead
request the individual clocks in the driver. For i.MX there are
generally three different clocks:

ipg: bus clock (needed to access registers)
ahb: dma relevant clock, sometimes referred to as hclk in the datasheet
per: bit clock, pixel clock

This patch changes the driver to request the individual clocks.
Currently all clk_get will get the same clock until the SoCs
are converted to the generic clock framework
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
      52dac615
  35. 21 4月, 2012 1 次提交
  37. 05 3月, 2012 1 次提交
    • S
      mmc: sdhci-esdhc-imx: fix for mmc cards on i.MX5 · 5b6b0ad6
      由 Sascha Hauer 提交于 
      On i.MX53 we have to write a special SDHCI_CMD_ABORTCMD to the
SDHCI_TRANSFER_MODE register during a MMC_STOP_TRANSMISSION
command. This works for SD cards. However, with MMC cards
the MMC_SET_BLOCK_COUNT command is used instead, but this
needs the same handling. Fix MMC cards by testing for the
MMC_SET_BLOCK_COUNT command aswell. Tested on a custom i.MX53
board with a Transcend MMC+ card and eMMC.

The kernel started used MMC_SET_BLOCK_COUNT in 3.0, so this
is a regression for these boards introduced in 3.0; it should
go to 3.0/3.1/3.2-stable.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Cc: <stable@vger.kernel.org>
Signed-off-by: NChris Ball <cjb@laptop.org>
      5b6b0ad6
  39. 01 2月, 2012 1 次提交
  41. 12 1月, 2012 1 次提交
  43. 20 12月, 2011 1 次提交
  45. 11 11月, 2011 1 次提交
    • S
      arm/imx: fix imx6q mmc error when mounting rootfs · f750ba9b
      由 Shawn Guo 提交于 
      The following error is seen in some case when mounting rootfs from
SD/MMC cards.

  Waiting for root device /dev/mmcblk0p1...
  mmc1: host does not support reading read-only switch. assuming write-enable.
  mmc1: new high speed SDHC card at address b368
  mmcblk0: mmc1:b368 SDC   3.74 GiB
   mmcblk0: p1
  mmc1: Timeout waiting for hardware interrupt.
  mmcblk0: error -110 transferring data, sector 3678224, nr 40, cmd response 0x900, card status 0xc00
  end_request: I/O error, dev mmcblk0, sector 3678225
  Buffer I/O error on device mmcblk0p1, logical block 458754
  lost page write due to I/O error on mmcblk0p1

This patch fixes the problem by lowering the usdhc clock and correcting
watermark configuration.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Chris Ball <cjb@laptop.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
      f750ba9b