The entries are separated as ARM V4/V5 and ARM V7 as some other per-SoC config
options may be removed in the near future.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Signed-off-by: NOlof Johansson <olof@lixom.net>

The Kconfig symbol DEBUG_MVEBU_UART_ALTERNATE was renamed to
DEBUG_MVEBU_UART0_ALTERNATE. And the symbol DEBUG_MVEBU_UART1_ALTERNATE
was added to allow UART1 as a DEBUG_LL target. Make the comment at the
top of this DTS reflect those changes.

Since we're touching this DTS add comments to show which blocks describe
UART0 and UART1.
Signed-off-by: NPaul Bolle <pebolle@tiscali.nl>
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>

Add the regulators to each SATA port.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

The pogoplug differs from the SheevaPlug only by a
few details, but especially in the led assignments.
This patch was tested under Gentoo Linux and is
based on dts files from Arch Linux ARM and OpenWrt.
Suggested-by: NFelix Kaechele <heffer@fedoraproject.org>
Suggested-by: NOleg Rakhmanov <moonman.ca@gmail.com>
Signed-off-by: NChristoph Junghans <ottxor@gentoo.org>
[Andrew Lunn <andrew@lunn.ch>: Fixed subject line]
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>

Add dts file for Hisilicon hip01 ca9x2 board
Signed-off-by: NWang Long <long.wanglong@huawei.com>
Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
[olof: Folded in smp enable-method from a different patch]
Signed-off-by: NOlof Johansson <olof@lixom.net>

Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>

Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>

It was accidentally left (& copied & pasted all around) from our
experiments with gpio-keys-polled.
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>

Luxul XWC-1000 is a controller device based on BCM4708 SoC. The only
unusual thing in its DTS file is "ubi" partition on NAND flash.
Signed-off-by: NDan Haab <dhaab@luxul.com>
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>

These add device tree entry for qspi device on dra72-evm.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This patch adds the uart ports and the uart clock to Mediateks
mt6592 SoC.
Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>

Seems to be a left-over from an automatic merge.
Signed-off-by: NMichael Heimpold <mhei@heimpold.de>
Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

On Vybrid, all peripherals are numbered starting with zero,
including the GPIO and PORT module. However, the labels of the
corresponding device tree nodes start with one, which is confusing.
Fix that by renaming the labels of the gpio nodes in the device
tree.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Enable dma support for ecspi5 controller
Signed-off-by: NAnton Bondarenko <anton_bondarenko@mentor.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The file is roughly sorted alphabetically (with some exceptions where
old options have been split in two), so alphascale should go at the
top instead of at the bottom.

Also linewrap like other entries have been lately.
Signed-off-by: NOlof Johansson <olof@lixom.net>

for now it is wary basic SoC description with most important IPs needed
to make this device work
Signed-off-by: NOleksij Rempel <linux@rempel-privat.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This allows booting the device with basic functionality.

Note that at least on my revision c board the DDR3 does
not seem to work properly and only some of the memory
can be reliably used.

Also, the mainline u-boot does not seem to properly
initialize the ethernet, so I've been using the old TI
u-boot at:

http://arago-project.org/git/projects/?p=u-boot-omap3.git;a=summary

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The clocks on dm816x are a bit different from the other omap
variants. The clocks are sourced from a FAPLL (Flying Adder PLL)
unlike on other omaps. Other than that, it's a similar setup
to am33xx with extra muxes and dividers that can be defined
as existing component clocks.

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Similar to other omap variants, let's add dm816x support.

Note that this is based on generated data from the
TI81XX-LINUX-PSP-04.04.00.02 patches published at:

http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html

I've verified the basic functionality, but have not been
able to test all the devices on dm8168-evm.

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The interrupt is 16, not 32 (which it would be if we include PPIs
in the count of interrupts).

Cc: Andy Gross <agross@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NAndy Gross <agross@codeaurora.org>
Tested-by: NAndy Gross <agross@codeaurora.org>
Signed-off-by: NKumar Gala <galak@codeaurora.org>

This changes muxes in gpio26 pin to function as gpio and adds support
for sd card detect for apq8064 based IFC6410 board.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NPramod Gurav <pramod.gurav@smartplayin.com>
Signed-off-by: NKumar Gala <galak@codeaurora.org>

The MiPHY28lp is a Generic PHY which can serve various SATA, PCIe or
USB3 devices. The two first ports can be use for either; both SATA, both
PCIe or one of each in any configuration.
The Third port is only for USB3.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

B2199 HDK is the reference board for STiH418 SoC.
It has the following characteristics:
 - 3GB DDR3
 - 8GB eMMC / SD-Card slot
 - 32MB NOR Flash
 - 1 x Gbit Ethernet
 - 1 x USB3.0 port
 - 2 x USB2.0 ports
 - 1 x Sata or Mini-PCIe port
 - 1 x WiFi 802.11ac (Quantenna)
 - 1 x HDMI out
 - 1 x HDMI in
 - 1 x SPDIF
Reviewed-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

The STiH418 is advanced UHD 60fps AVC processor with 3D graphic acceleration and
quad-core ARM Cortex A9 CPU.
Reviewed-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

This patch adds the DRM/KMS dt nodes.
Signed-off-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org>
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

This patch adds the DRM/KMS dt nodes.
This node can't be in stih407-family.dtsi file because in the future we
will integrate a new stih418-b2199 board. It's a stih407 family board
with different drm/kms dt nodes.
That is why i created the stih407.dtsi file.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

According to v4l2 dt document, we add:
  a camera host: ISI port.
  a i2c camera sensor: ov2640 port.
to sama5d3xmb.dtsi.

The ov2640 node defines the pinctrls, clocks and refer to isi port.
The ISI node also has a reference to the ov2640 port.
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

For sama5d3xmb board, the pins: pinctrl_isi_pck_as_mck is pck1, and
used to provide MCK for camera sensor.

We change its name to: pinctrl_pck1_as_isi_mck.

As we want camera sensor instead of ISI to configure the pck1 (ISI_MCK) pin.
So we remove this pinctrl from ISI DT node. It will be added in sensor's
DT node.
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

For sama5d3xmb board, the pins: pinctrl_isi_{power,reset} is used to
power-down or reset camera sensor.
So we should let camera sensor instead of ISI to configure the pins.

This patch will change pinctrl name from pinctrl_isi_{power,reset} to
pinctrl_sensor_{power,reset}. And remove these two pinctrl from ISI's
DT node. We will add these two pinctrl to sensor's DT node.
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The mck is decided by the board design, move it to mb related
dtsi file.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The ISI has 12 data lines, add the missing two data lines.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

As the ISI has 12 data lines, however we only use 8 data lines with
sensor module. So, split the data line into two groups which make
it can be choosed depends on the hardware design.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Add ISI peripheral clock in sama5d3.dtsi.
Signed-off-by: NJosh Wu <josh.wu@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The ethernut5 is actually based on an at91sam9xe, use the correct dts include.

Cc: Martin Reimann <martin.reimann@egnite.de>
Cc: Tim Schendekehl <tim.schendekehl@egnite.de>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

at91sam9xe is slightly different from at91sam9260, in particular it has a
different SRAM size and location.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Add nodes for the SRAM available on atmel SoCs
For the at91sam9260 and the at91sam9g20, address mirroring is used to create a
single contiguous SRAM range instead of declaring two separate banks.

Also remove leftover TODOs in the sam9g45 file
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
[nicolas.ferre@atmel.com: correct at91sam9rl sram size => 0x10000]
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Enable the RTC on the at91rm9200ek.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Add a node for the RTC available on at91rm9200.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Add node for the RTC available on the at91sam9n12.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>