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  1. 01 5月, 2009 2 次提交
  3. 23 4月, 2009 1 次提交
  5. 07 4月, 2009 1 次提交
  7. 24 3月, 2009 1 次提交
  9. 11 3月, 2009 3 次提交
  11. 09 3月, 2009 1 次提交
  13. 15 2月, 2009 1 次提交
  15. 29 1月, 2009 1 次提交
    • K
      powerpc/fsl-booke: Cleanup init/exception setup to be runtime · 105c31df
      由 Kumar Gala 提交于 
      We currently have a few variants of fsl-booke processors (e500v1, e500v2,
e500mc, and e200).  They all have minor differences that we had previously
been handling via ifdefs.

To move towards having this support the following changes have been made:

* PID1, PID2 only exist on e500v1 & e500v2 and should not be accessed on
  e500mc or e200.  We use MMUCFG[NPIDS] to determine which case we are
  since we only touch PID1/2 in extremely early init code.

* Not all IVORs exist on all the processors so introduce cpu_setup
  functions for each variant to setup the proper IVORs that are either
  unique or exist but have some variations between the processors
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      105c31df
  17. 21 12月, 2008 2 次提交
  19. 06 12月, 2008 1 次提交
  21. 17 10月, 2008 1 次提交
  23. 20 8月, 2008 1 次提交
  25. 26 7月, 2008 1 次提交
  27. 25 7月, 2008 1 次提交
  29. 22 7月, 2008 1 次提交
    • T
      powerpc: Indicate which oprofile counters to use while in compat mode · 79e25bac
      由 Torez Smith 提交于 
      While running on a system with new hardware and a kernel where the
cpu_specs[] table does not recognize the new hardware, the identify_cpu()
routine will select the default case as it searches through cpu_specs[]
in an attempt to match the real PVR. Once the default case is selected,
non of the oprofile counters and/or fields have been set up or defined.

When identify_cpu() is called once more with the logical PVR, some of
the cpu specific fields are replaced with the exception of the oprofile
related ones. However, in the case where we have actually taken the
default case while searching for the real PVR, we need to tell
oprofile that we are now running in compatibility mode so it can pick up
the correct counters. We do this by setting the oprofile_cpu_type field
to be that taken from the cpu_specs[] for the cpu we are now emulating.

This change will detect that we are now altering the real PVR and determine
if we also need to update the oprofile_cpu_type field.
Signed-off-by: NTorez Smith <lnxtorez@linux.vnet.ibm.com>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      79e25bac
  31. 15 7月, 2008 1 次提交
    • N
      powerpc: Add PPC_FEATURE_PSERIES_PERFMON_COMPAT · 0f473314
      由 Nathan Lynch 提交于 
      Background from Maynard Johnson:
As of POWER6, a set of 32 common events is defined that must be
supported on all future POWER processors.  The main impetus for this
compat set is the need to support partition migration, especially from
processor P(n) to processor P(n+1), where performance software that's
running in the new partition may not be knowledgeable about processor
P(n+1).  If a performance tool determines it does not support the
physical processor, but is told (via the
PPC_FEATURE_PSERIES_PERFMON_COMPAT bit) that the processor supports
the notion of the PMU compat set, then the performance tool can
surface just those events to the user of the tool.

PPC_FEATURE_PSERIES_PERFMON_COMPAT indicates that the PMU supports at
least this basic subset of events which is compatible across POWER
processor lines.
Signed-off-by: NNathan Lynch <ntl@pobox.com>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      0f473314
  33. 04 7月, 2008 1 次提交
  35. 01 7月, 2008 3 次提交
  37. 30 6月, 2008 1 次提交
  39. 26 6月, 2008 1 次提交
  41. 19 6月, 2008 1 次提交
    • K
      powerpc/booke: Add support for new e500mc core · 3dfa8773
      由 Kumar Gala 提交于 
      The new e500mc core from Freescale is based on the e500v2 but with the
following changes:

* Supports only the Enhanced Debug Architecture (DSRR0/1, etc)
* Floating Point
* No SPE
* Supports lwsync
* Doorbell Exceptions
* Hypervisor
* Cache line size is now 64-bytes (e500v1/v2 have a 32-byte cache line)
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      3dfa8773
  43. 11 6月, 2008 1 次提交
  45. 12 5月, 2008 1 次提交
  47. 09 5月, 2008 1 次提交
  49. 25 4月, 2008 1 次提交
  51. 26 3月, 2008 1 次提交
    • S
      [POWERPC] 4xx: Add AMCC 460EX/460GT support to cputable.c & cpu_setup_44x.S · 464076a4
      由 Stefan Roese 提交于 
      This patch adds basic support for the AMCC 460EX/460GT PPC's to arch/powerpc.
Currently those PPC's are still based on a 440 core and *not* a 460 core.

Here some basic features of those SoC's:

460EX:
- Up to 1.2GHz, 32kB L1 I-cache and D-cache, 256kB L2-cache, FPU
- 1 * PCI (max 66MHz), 2 * PCIe (one 4-lane, one 1-lane)
- 2 * GBit Ethernet with TCP/IP acceleration
- USB 2.0 Host/Device OTG and Host interface
- SATA controller
- Optional security feature

460GT (only changes to 460EX):
- 4 * GBit Ethernet with TCP/IP acceleration
- RapidIO
- No SATA
- No USB
Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
      464076a4
  53. 06 2月, 2008 2 次提交
  55. 25 1月, 2008 2 次提交
  57. 24 12月, 2007 3 次提交
  59. 12 12月, 2007 1 次提交