The asm version is 4.4 times faster than the generic C version and
10X smaller in code size.
Signed-off-by: NKen Chen <kenneth.w.chen@intel.com>
Signed-off-by: NTony Luck <tony.luck@intel.com>

Additional updates to conform with Rev 2.2 of Volume 2 of "Intel
Itanium Architecture Software Developer's Manual" (January 2006).

Add pal_bus_features_s bits 52 & 53 (page 2:347)
Add pal_vm_info_2_s field max_purges (page 2:2:451)
Add PAL_GET_HW_POLICY call (page 2:381)
Add PAL_SET_HW_POLICY call (page 2:439)

Sample output before:
---------------------------------------------------------------------
cobra:~ # cat /proc/pal/cpu0/vm_info
Physical Address Space         : 50 bits
Virtual Address Space          : 61 bits
Protection Key Registers(PKR)  : 16
Implemented bits in PKR.key    : 24
Hash Tag ID                    : 0x2
Size of RR.rid                 : 24
Supported memory attributes    : WB, UC, UCE, WC, NaTPage
---------------------------------------------------------------------

Sample output after:
---------------------------------------------------------------------
cobra:~ # cat /proc/pal/cpu0/vm_info
Physical Address Space         : 50 bits
Virtual Address Space          : 61 bits
Protection Key Registers(PKR)  : 16
Implemented bits in PKR.key    : 24
Hash Tag ID                    : 0x2
Max Purges                     : 1
Size of RR.rid                 : 24
Supported memory attributes    : WB, UC, UCE, WC, NaTPage
---------------------------------------------------------------------

Signed-off-by: Russ Anderson (rja@sgi.com)
Signed-off-by: NTony Luck <tony.luck@intel.com>

Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's
Manual" (January 2006) adds a se bit to the Processor State Parameter
fields (pages 2:299).  This patch gets the structs back in sync
with the spec.

Signed-off-by: Russ Anderson (rja@sgi.com)
Signed-off-by: NTony Luck <tony.luck@intel.com>

Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's
Manual" (January 2006) adds a dp bit to the cache_check and bus_check
fields (pages 2:401-2:404).  This patch gets the structs back in sync
with the spec.

Signed-off-by: Russ Anderson (rja@sgi.com)
Signed-off-by: NTony Luck <tony.luck@intel.com>

Changes and updates.

1. Remove fake rendz path and related code according to discuss with Khalid Aziz.
2. fc.i offset fix in relocate_kernel.S.
3. iospic shutdown code eoi and mask race fix from Fujitsu.
4. Warm boot hook in machine_kexec to SN SAL code from Jack Steiner.
5. Send slave to SAL slave loop patch from Jay Lan.
6. Kdump on non-recoverable MCA event patch from Jay Lan
7. Use CTL_UNNUMBERED in kdump_on_init sysctl.
Signed-off-by: NZou Nan hai <nanhai.zou@intel.com>
Signed-off-by: NTony Luck <tony.luck@intel.com>

Any code that relies on the volatile would be a bug waiting to happen
anyway.

Don't encourage people to think that putting 'volatile' on data
structures somehow fixes problems.  We should always use proper locking
(and other serialization) techniques.
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

This is a resubmission of patches originally created by Ingo Molnar.
The link below is the initial (?) posting of the patch.

  http://marc.theaimsgroup.com/?l=linux-kernel&m=115217423929806&w=2

Remove 'volatile' from spinlock_types as it causes GCC to generate bad
code (see link) and locking should be used on kernel data.
Signed-off-by: NArt Haas <ahaas@airmail.net>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Import many updates from i386's i8259.c, especially genirq transitions.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This patch adds missing parenthesis around 'dir' argument in pte_offset()
macro definition.

It also removes an extra space in the definition of pte_offset_kernel()
macro.
Signed-off-by: NFranck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The first patch is to the 2.6 kernel include file (for m68knommu), to get
rid of the conditional definitions, otherwise the structures have different
sizes depending on whether there's an FPU or not.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Add a null definition for irq_canonicalize(). It is used in the gerneric
serial subsystem code, can't compile without it.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

This adds support for RTCs (through genrtc) for M68KNOMMU.

Board-specific code will have to link the appropriate RTC driver to the
mach_hwclk callback, at minimum.
Signed-off-by: NGavin Lambert <gavinl@compacsort.com>
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Signed-Off-By: NDavid Howells <dhowells@redhat.com>

The following moves the creation of IPR interupts into setup-7750.c
and updates a few other things to make it all work after the "Drop
CPU subtype IRQ headers" commit. It boots and runs fine on my titan
board.

 - adds an ipr_idx to the ipr_data and uses a function in the subtype
   code to calculate the address of the IPR registers

 - adds a function to enable individual interrupt mode for externals
   in the subtype code and calls that from the titan board code
   instead of doing it directly.

 - I changed the shift in the ipr_data to be the actual # of bits to
   shift, instead of the numnber / 4 - made it easier to match with
   the manual.
Signed-off-by: NJamie Lenehan <lenehan@twibble.org>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

When hugetlbpage support isn't enabled, this can be bogus.
Wrap it back in _PAGE_FLAGS_HARD to avoid changes to the
base PTE when not aiming for larger sizes.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Wire up all of the essentials for lockdep..
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

gcc4 gets a bit pissy about the outputs:

include/asm/atomic.h: In function 'atomic_add':
include/asm/atomic.h:37: error: invalid lvalue in asm statement
include/asm/atomic.h:30: error: invalid lvalue in asm output 1
...

this ended up being a thinko anyways, so just fix it up.

Verified for proper behaviour with the older toolchains, too.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds basic NO_IDLE_HZ support to the SH timer API so timers
are able to wire it up. Taken from the ARM version, as it fit in
to our API with very few changes needed.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This syncs up the SH clock framework with the linux/clk.h API,
for which there were only some minor changes required, namely
the clk_get() dev_id and subsequent callsites.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

There were a number of places that made evil PAGE_SIZE == 4k
assumptions that ended up breaking when trying to play with
8k and 64k page sizes, this fixes those up.

The most significant change is the way we load THREAD_SIZE,
previously this was done via:

	mov	#(THREAD_SIZE >> 8), reg
	shll8	reg

to avoid a memory access and allow the immediate load. With
a 64k PAGE_SIZE, we're out of range for the immediate load
size without resorting to special instructions available in
later ISAs (movi20s and so on). The "workaround" for this is
to bump up the shift to 10 and insert a shll2, which gives a
bit more flexibility while still being much cheaper than a
memory access.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This extends the SH DMA API for allowing handling of DMA
channels based off of their respective capabilities.

A couple of functions are added to the existing API,
the core bits are register_chan_caps() for registering
channel capabilities, and request_dma_bycap() for fetching
a channel dynamically based off of a capability set.
Signed-off-by: NMark Glaisher <mark.glaisher@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Two of the fields in /proc/[number]/stat are documented in
proc(5) as:

      kstkesp %lu
	     The current value of esp (stack pointer), as
	     found in the kernel stack page for the process.

      kstkeip %lu
	     The current EIP (instruction pointer).

The SH currently prints the the last SP and PC of the process
inside the kernel, while most other archs use the last user
space values.

This patch modifes the SH to display the user space values.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Handle simple TLB miss faults which can be resolved completely
from the page table in assembler.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds support for a generic push switch framework. Adaptable for
various switches, including GPIO switches and the push switches commonly
found on Renesas debug boards.

This allows switch states to be trivially reported through sysfs.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Remove extra bits from the pmd structure and store a kernel logical
address rather than a physical address. This allows it to be directly
dereferenced. Another piece of wierdness inherited from x86.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Add TTB accessor functions and give it a sensible default
value. We will use this later for optimizing the fault
path.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Remove the previous saving of fault codes into the thread_struct
as they are never used, and appeared to be inherited from x86.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds some preliminary support for the SH-X2 MMU, used by
newer SH-4A parts (particularly SH7785).

This MMU implements a 'compat' mode with SH-X MMUs and an
'extended' mode for SH-X2 extended features. Extended features
include additional page sizes (8kB, 4MB, 64MB), as well as the
addition of page execute permissions.

The extended mode attributes are placed in a second data array,
which requires us to switch to 64-bit PTEs when in X2 mode.

With the addition of the exec perms, we also overhaul the mmap
prots somewhat, now that it's possible to handle them more
intelligently.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Simple 7785 placeholders to start hooking up other bits of code.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This drops the various IRQ headers that were floating around
and primarily providing hardcoded IRQ definitions for the
various CPU subtypes. This quickly got to be an unmaintainable
mess, made even more evident by the subtle breakage introduced
by the SH-2 and SH-2A changes.

Now that subtypes are able to register IRQ maps directly, just
rip all of the headers out.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

A number of API changes happened underneath the 7206 patches, update
for everything that broke.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Mostly SH-2 wrappers..
Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Fix up arch-specific work items where possible to use the new work_struct and
delayed_work structs.

Three places that enqueue bits of their stack and then return have been marked
with #error as this is not permitted.
Signed-Off-By: NDavid Howells <dhowells@redhat.com>

CONFIG_LBD and CONFIG_LSF are spread into asm/types.h for no particularly
good reason.

Centralising the definition in linux/types.h means that arch maintainers
don't need to bother adding it, as well as fixing the problem with
x86-64 users being asked to make a decision that has absolutely no
effect.

The H8/300 porters seem particularly confused since I'm not aware of any
microcontrollers that need to support 2TB filesystems.
Signed-off-by: NMatthew Wilcox <matthew@wil.cx>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

s->functions needs to be initialized earlier, for the "let's see
how high it increases" approach means that pcmcia_request_irq()
(which makes use of this value) is confused, and might request
an exclusive IRQ first even though it is not supposed to.

Also, a CIS override autoloaded using the firmware loader may
allow for the use of more or less functions in a multifunction
card. Therefore, we may need to schedule a call to add this
second function later on, or simply remove the other function
(it's always the first -valid- function which reaches this
codepath).

Many thanks to Fabrice Bellet for debugging and testing patches.
Signed-off-by: NDominik Brodowski <linux@dominikbrodowski.net>

Also the R4000 / R4600 LL/SC instructions imply a sync so no explicit sync
needed.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

For the definition of atomic64_t atomic.h was relying on <asm/types.h>
having been included previously.  Before changeset
d89d8e0637a5e4e0a12e90c4bc934d0d4c335239 this was happening as a
side effect of including <linux/spinlock.h>.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

N32 SysV IPC system calls should use 32-bit compatible code.
arch/mips/kernel/linux32.c have similar compatible code for O32, but
ipc/compat.c seems more complete.  We can use it for both N32 and O32.

This patch should fix these problems (and other possible problems):

http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=1149188824.6986.6.camel%40diimka-laptop
http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=44C6B829.8050508%40caviumnetworks.comSigned-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NMariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

OK, that seems to be enough to deal with the mess.
Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>