- 04 2月, 2009 1 次提交
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由 Michael Hennerich 提交于
Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com> Signed-off-by: NBryan Wu <cooloney@kernel.org>
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- 07 1月, 2009 1 次提交
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由 Graf Yang 提交于
Blackfin dual core BF561 processor can support SMP like features. https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-like In this patch, we provide SMP extend to BF561 kernel code Signed-off-by: NGraf Yang <graf.yang@analog.com> Signed-off-by: NMike Frysinger <vapier.adi@gmail.com> Signed-off-by: NBryan Wu <cooloney@kernel.org>
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- 27 8月, 2008 1 次提交
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由 Bryan Wu 提交于
Signed-off-by: NBryan Wu <cooloney@kernel.org>
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- 07 5月, 2008 1 次提交
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由 Michael Hennerich 提交于
Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com> Signed-off-by: NBryan Wu <cooloney@kernel.org>
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- 25 4月, 2008 1 次提交
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由 Michael Hennerich 提交于
Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com> Signed-off-by: NBryan Wu <cooloney@kernel.org>
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- 24 4月, 2008 1 次提交
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由 Graf Yang 提交于
[Blackfin] arch: Resolve the clash issue of UART defines between blackfin headers and include/linux/serial_reg. Signed-off-by: NGraf Yang <graf.yang@analog.com> Cc: Robin Getz <rgetz@blackfin.uclinux.org> Signed-off-by: NBryan Wu <cooloney@kernel.org>
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- 15 11月, 2007 1 次提交
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由 Mike Frysinger 提交于
VDSP has double fault on core a/b inverted for BF561 -- bit 11 is core a while bit 12 is core b Signed-off-by: NMike Frysinger <michael.frysinger@analog.com> Signed-off-by: NBryan Wu <bryan.wu@analog.com>
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- 13 11月, 2007 1 次提交
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由 Mike Frysinger 提交于
Blackfin arch: add a compatible DOUBLE_FAULT define to enable resets on double faults in either core Signed-off-by: NMike Frysinger <michael.frysinger@analog.com> Signed-off-by: NBryan Wu <bryan.wu@analog.com>
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- 30 10月, 2007 1 次提交
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由 Mike Frysinger 提交于
Signed-off-by: NMike Frysinger <michael.frysinger@analog.com> Signed-off-by: NBryan Wu <bryan.wu@analog.com>
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- 11 10月, 2007 1 次提交
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由 Bryan Wu 提交于
Blackfin arch: add TWIx_REGBASE and SPIx_REGBASE to specific CPU header files, use the new REGBASE for board platform resources Signed-off-by: NBryan Wu <bryan.wu@analog.com>
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- 24 7月, 2007 1 次提交
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由 Mike Frysinger 提交于
setup aliases for some core Core A MMRs to ease porting in cases where common code would actually want Core A (or Core B MMR is reserved) Signed-off-by: NMike Frysinger <michael.frysinger@analog.com> Signed-off-by: NBryan Wu <bryan.wu@analog.com>
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- 22 5月, 2007 1 次提交
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由 Bryan Wu 提交于
a) add new processor BF52x/BF54x header files b) update blackfin BF533/BF537/BF561 header files to latest one in VDSP. c) scrub watchdog/rtc masks from headers as we dont need/want them (too generic and the drivers dont use them) Signed-off-by: NMike Frysinger <michael.frysinger@analog.com> Signed-off-by: NRoy Huang <roy.huang@analog.com> Signed-off-by: NSonic Zhang <sonic.zhang@analog.com> Signed-off-by: NBryan Wu <bryan.wu@analog.com> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 08 5月, 2007 1 次提交
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由 Bryan Wu 提交于
This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: NBryan Wu <bryan.wu@analog.com> Signed-off-by: NMariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: NAubrey Li <aubrey.li@analog.com> Signed-off-by: NJie Zhang <jie.zhang@analog.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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